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RE: Clause 51 (XSBI) questions

Erik, all,

Being one of Justins "et al"'s, I've filled in some answers below.

Kind regards

Henning Lysdal

Henning Lysdal			Tel.: +45 70 10 10 62
Datacom Design Manager		Direct: +45 44 54 61 54
					Fax: +45 70 10 10 63
GiGA ApS - an Intel Company
Mileparken 22			e-mail: henning.lysdal@xxxxxxxxx
2740 Skovlunde			web:

-----Original Message-----
From: Erik Trounce [mailto:erikt@xxxxxxxxxxxxxxxxxx]
Sent: 11. oktober 2000 23:29
Subject: Clause 51 (XSBI) questions

Justin, et al

I have some comments and questions regarding clause
51, the XSBI interface.

1. Table 5-6 of the draft 1.0 specifies a maximum delay
variation of 30 ns p-p.  Does the condition (frequency <
1kHz) refer to the frequency of the delay variation
changing? or is there some other meaning.
<<<<<<<<<< ANSWER >>>>>>>>>>
The condition refers to the frequency of the delay variation. The < 1kHz
range contains delay variations over such phenomena as temperature and
process (static, but different for each PCS chip).

2. In section 51.3.1 it says: "The falling edge of
PMA_TXCLK_SRC<0,1> is used by the PCS to derive
PMA_TX_CLK<0,1>.  Does this mean we are meant to invert
PMA_TXCLK_SRC to create PMA_TX_CLK?  or is it meant to be
a requirement that if a PLL is used, the PLL uses the
negative TXCLK_SRC edge for phase alignment?
<<<<<<<<< ANSWER >>>>>>>>>>>>
Good point. This specification is not necessary. As long as you meet the
timing requirements shown in figure 51-4 the system is supposed to work. I
suggest we remove this sentence and also that we do not specify the details
of PLL operation. This is sufficient to ensure interoperability and leaves
room for innovative implementations.

3. The draft spec specifies the transmit direction timing
at the PMA inputs.  There are no numbers for the PCS outputs.
Furthermore, the values given for setup and hold are 50 ps
smaller than OIF SFI-4 specifies at the SERDES input.  Will
802.3 ever specify timing constraints at the PCS output for
the transmit direction and PMA input for the receive direction?
<<<<<<<<<<<< ANSWER >>>>>>>>>>
The interfaces are specified at the PMA input for transmit and the PCS input
for receive. The input timing (on both PCS and PMA) is described using setup
and hold times. If we choose to add an output timing this should be
specified in terms of ck-data delay. The details of the timing specification
are of course subject to discussion. In the draft we have chosen to tighten
the requirements for the PMA and leave a larger timing-budget for the PCS
and the board. The PMA devices are fabricated in high-speed technologies
whereas the PCS is standard CMOS or FPGAs.

4. Is there a reason the edges are reversed between OIF SFI-4
and the draft 1.0?  Specifically, SFI-4 specifies the Rx data
valid around the RX_CLK positive edge while the draft
specifies Rx data valid around the RX_CLK falling edge.  I
realize you can simply switch your differential inputs to
achieve the switch.
<<<<<<<<<<<<<< ANSWER >>>>>>>>>>>>
The interface timing is specified as an input timing requirement using setup
and hold times. Positioning the falling edge of the clock in the center of
the databit implies that data is latched out of the PMA device on the rising
edge. The OIF framer input and SerDes output spec requires system
implementors to invert the recieve clock on the board. For clarity we have
chosen to change the sign in the actual specification, so no
clock-inversions are required by system implementors.

Erik Trounce