Re: wis scrambler vs 64/66 scrambler
I beleive the fundamental difference between the two types of scramblers
(other than the fact that they have different polynomials) is that the
64b/66b is a self-synchronous scrambler, relying on the fact that the
input data affects the value shifted into the LFSR bank.
Because of this, the 64b/66b scrambler does not need to be reset, and
will synchronize itself properly after 58 clock cycles (in serial
implementation) or 1 clock cycle (in a parallel implementation).
The WIS scrambler on the other hand needs to be reset following the last
Z0 octet in each WIS frame. Also notice that the input now does not feed
into the bank of LFSR registers. The LFSR can be viewed as independent
of the input, where the LFSR output is XORed with the input signal to
create the output signal. Because of this structure, the behavior of the
LFSR is completely predetermined, and it goes through 127 cycles before
repeating itslef. It is reset to all 1's because the all 0's value would
result in a static case, and thus should be avoided. The WIS scrambler
is NOT self-synchronous. That is the difference.
Eric Ng wrote:
> In the blue book the wis scrambler is x7+x6+1, only the
> 6th and 7th term are xor and feedback to the beginning
> of the 7-bit shift register.
> However, in the 64/66PCS section x58+x19+1 is used but
> this time the scrambled output xor 58th xor 19th and
> feed back to the beginning of the 58-bit shift registers.
> The two equations are very similar but the drawing in the
> bluebook suggested otherwise. Also, base on the drawing,
> the wis scrambler/descrambler would be the same while the
> 64/66 scrambler and descrambler are different. I must have
> misunderstood some fundamental. I hope someone could clarify
> this for me.
> Thanks in advance.
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