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64b/66b scrambler


I have some questions on the 64b/66b scrambler.  
In sec 49.2.6 of draft D1.0 stated that there is no 
reqiurement on the initial value.  Please correct me 
if I'm wrong.  The descrambler can recover 58th bit 
by doing S0^S39^S58 and so do the subsequent bits. 

What happen at power up or the system is reset?  Are we 
assuming that the first few frames will be used for
synchronization?  That we will be well over the first
58bits by the time, the first valid payload is recevied.

Also, once the scrambler/descarmbler are initialized at
power up or system reset, the shift register will not
reset at packet boundary and/or SPE boundary.  

In the bluebook, the sample test vector, the scrambler
is initialized to all 1's.  Is this the default value 
at power up reset?

Thanks in advance.

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