| Thread Links | Date Links | ||||
|---|---|---|---|---|---|
| Thread Prev | Thread Next | Thread Index | Date Prev | Date Next | Date Index |
I need some clarification to the obvious. I see in clause 51 references to PMA_TX_CLK<0,1>, PMA_TXCLK_SRC<0,1>, and PMA_RX_CLK<0,1>. Is it correct to assume that <0> refers to (tx/rx)_data_group<7:0> and <1> refers to (tx/rx)_data_group<15:8>, in other words each byte has its own synchronizing clock? If that is the case, do we need two separate clocks on each direction?
Thank you,
Rick Rabinovich
Rick Rabinovich
Hardware Group Lead Engineer
System Architect
Spirent Communications
26750 Agoura Road
Calabasas, CA 91302
Phone: 818-676-2476
Fax : 818-880-9293
Email: rick.rabinovich@xxxxxxxxxxxxxx