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RE: XAUI receiver characteristics


Comments below.

>OK I see how it is set up. Having a larger total jitter budget
>for the transmitter is better than adding specified jitter 
>components. 0.3UI jitter due to frequency dependent
>attenuation seems adequate for the 50cm distance range. 
>Jitter masks are difficult to specify and to measure. On top
>of the jitter produced by the transmitter into a perfect termination,
>we should account for contribution from reflections and folding
>of common mode reflections into the differential domain. 

0.3UI allows for all of the above effects. The 20" PCB trace pair itself
(well balanced, shielded and matched) will introduce about half of this. 

>Could all this and even the output impedance specification be replaced
>by a jitter measurement at the end of one or two realistic load

Perhaps it could, but the result might be components from different
designers that do not meet the jitter budget when put together. For example,
one designer controls impedance very tightly and lets RJ be larger in his
transmitter/receiver pair, while another controls RJ and relaxes impedance
control. Putting the two together results in large RJ and poor return loss
simultaneously, breaking the link. I think it is better to specify return
loss separately and include such issues as you've raised above in the
justification for the jitter budget and eye. Does this sound reasonable?

>> Assuming the 0.65 receive jitter number for now, would the 
>> following satisfy your concern? If not, can you propose something?
>> "The XAUI receiver shall have a peak-to-peak jitter amplitude 
>> tolerance of 0.65 UI. It is recommended that the tolerance be 
>> at least 6.5 UI below TBD kHz."
>Jitter tolerance specifications involve characteristics of the
>data recovery. Is there a desire for the XAUI specs to avoid
>going into specifications for this?

Yes, there is a very strong desire. One reason is that the standard must be
verifiable (i.e., measurable). Another is that the standard should not force
a particular implementation such as a CDR architecture.

>Where does the quote come from?

It is not a quote, but my suggestion for an addition to clause 47 to address
your concern. It is intended to provide some guidance to designers on where
to place the PLL pole and may help foster successful implementations. I
worded it as a recommendation instead of a requirement since it is not
critical to function and interoperability. This is the general philosophy
that I think most participants prefer - to specify only what is necessary.
Helpful details like this can then be included as recommendations and
informative statements. (It was for this same philosophical reason that I
made the suggestion that I did to Anne concerning receiver compliance and
minimum pulse width.)