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RE: Clause 51 (XSBI) questions : PMA_TXSRC_CLK

Title: RE: Clause 51 (XSBI) questions : PMA_TXSRC_CLK
Hi Rick,
We do specify PMA_TXCLK_SRC tolerance to +/- 100ppm (table 51-5).
PMA_TXCLK_SRC is the master clock for the PCS. The fact that the PMA most likely will require an external reference to generate PMA_TXCLK_SRC is a PMA implementation detail. During the spring we had long discussions about specifying the REFCLK, especially the frequency. However, we finally realized that REFCLK in the OIF SFI-4 interface (as we try to leverage) is only used by the SerDes. Thus, as long as we specify PMA_TXCLK_SRC, REFCLK is really an implementation detail of the SerDes. The SerDes vendor will have to take a long hard look at the PMA_TXCLK_SRC specification and at the serial transmit data jitter specification. Based on this SerDes vendors will most likely specify a crystal osc. for their device, but again this is implementation specific.
However, you make one very important point: PMA_TXCLK_SRC should always be present regardless of the link status. This also applies to PMA_RX_CLK.
Kind regards,
-----Original Message-----
From: Rabinovich, Rick [mailto:rick.rabinovich@xxxxxxxxxxxxxx]
Sent: 19. oktober 2000 03:38
To: 'Lysdal, Henning'; stds-802-3-hssg@xxxxxxxx
Subject: RE: Clause 51 (XSBI) questions : PMA_TXSRC_CLK

Hello Henning,

If the PMA_TX_CLK is derived from the PMA_TXCLK_SRC, it is fair to that assume that the PMA_TXCLK_SRC is generated from the PMA REFCLK and it will always be present regardless weather the link is up or down.

In addition, should we specify the PMA REFCLK frequency tolerance?

Rick Rabinovich
Hardware Group Lead Engineer
System Architect
Spirent Communications
26750 Agoura Road
Calabasas, CA 91302
Phone: 818-676-2476
Fax    : 818-880-9293
Email: rick.rabinovich@xxxxxxxxxxxxxx


-----Original Message-----
From: Lysdal, Henning [mailto:henning.lysdal@xxxxxxxxx]
Sent: Monday, October 16, 2000 12:12 AM
To: 'Jscquake@xxxxxxx'; stds-802-3-hssg@xxxxxxxx
Subject: RE: Clause 51 (XSBI) questions : PMA_TXSRC_CLK


I agree. You're wording is fine.

If no-one else has issues with this, let's move on to the next discussion.



-----Original Message-----
From: Jscquake@xxxxxxx [mailto:Jscquake@xxxxxxx]
Sent: 13. oktober 2000 20:15
To: henning.lysdal@xxxxxxxxx; erikt@xxxxxxxxxxxxxxxxxx;
Subject: Re: Clause 51 (XSBI) questions : PMA_TXSRC_CLK

Hello Henning,

Agreed on the need to use  the PMA_TXCLK_SRC as a reference for
the PCS. In that light I would modify (not REMOVE) section 51.3.1 line46 to
emphasize this need. new line to read

"The PMA_TXCLK_SRC is used by the PCS to derive the PMA_TX_CLK."

This comment was  previously mentioned on page 202 line 46/47 but I think
it is very worthwhile to repeat it again here.

We can take the details of the wording off line if the concept is agreed.


In a message dated 10/13/00 8:18:09 AM Pacific Daylight Time,
henning.lysdal@xxxxxxxxx writes:

>  Justin, Erik,

>  Much as we agree on must issues Justin, I have to disagree when you state
>  that "It is not required that one uses the PMA_TXCLK_SRC".

>  It is not required that the PCS use a specific edge of the PMA_TXCLK_SRC.
>  However, PMA_TXCLK_SRC is the primary clock source for the PCS (remember
>  that the reference clock for the PMA is not specified). Furthermore, if
>  PCS does not use the PMA_TXCLK_SRC, you open the loop thereby ruling out
>  PLL based timing control.

>  Regards,

>  Henning

Justin Chang
Quake Technologies, Inc.
50 Airport Parkway, San Jose, CA. 95110
Tel: 408-437-7723       email: justin@xxxxxxxxxxxxx
Fax: 408-437-4923       internet: