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Re: XGMII electricals


About 3 years ago I started the project for FC-HSPI to define the SSTL2
interface.  We started with JDEC and made few modifications.  With
of SSTL, I believe we can define the HSTL interface in more reasonable
frame.  If anybody is interested to see this document please go to FC
web site at and search for doc 99-251v3.  

XGMII interface in my view will be short lived.  But HSTL has more usage 
for high speed interface than just XGMII.  I made a presentation to FC
about 3 years ago if there is interest I can update it and make a


Ali Ghiasi

Yongbum Kim wrote:
> Dear Bob,
>         Thanks for detailed and insightful summary.  I like to
> add that our straw poll in New Orleans meeting was to indicate
> preferences.  We all agreed (w/o any discussions) that we will
> go back and study the issues and re-affirm SSTL or formalize HSTL 1.8V.
> In the mean time, we all agreed no draft change.  This includes the
> I/O technology and timing (source centered versus source sync.).
>         If the XGMII is viewed as more of short term, i.e. early
> 10G application, then it may not make sense to formalize 1.8V HSTL
> operation anyway, since today's technology would favor SSTL over HSTL.
> It is the anticipation of future mainstream CMOS technology that
> popularized a version of HSTL.  The industry will adopt outside of
> the scope of IEEE for these popular interfaces (good examples, RMII,
> SMII, RGMII, GBIC instead of exposed GMII, etc).
>         That said, I support leaving the spec. as SSTL.
> 1. Our industry has been resilient in adopting new I/O technology
>    when interface spec. out-lives the chosen I/O.
> 2. HSTL 1.8V is not a referenceable standard.
> 3. Between two problems: Backward compatibility and New specification
>    It is easier to design a new I/O cell that is backward compatible
>    than specifying I/O parameters that were never implemented.
> *. And although this should *NOT* be a standard body issues, but
>    multiple vendor implementations of XGMII (MAC and XAUI) are starting
>    to be available and their interoperability are being tested.
> regards,
> Yong.
> ======================================================
> Yongbum "Yong" Kim                  (408)570-0888 x141
> Chief Technical Officer             (408)570-0880  fax
> Allayer Technologies Corp.           ybkim@xxxxxxxxxxx
> 107 Bonaventura Drive 
> San Jose, CA 95134
> ==This Message is forwarded by RoX Switch at 1 Gb/s.==
> ======================================================
> -----Original Message-----
> From:   Grow, Bob [SMTP:bob.grow@xxxxxxxxx]
> Sent:   Wednesday, November 01, 2000 1:07 PM
> To:     'stds-802-3-hssg@xxxxxxxx'
> Subject:        XGMII electricals
> Implementing the XGMII concensus of the Task Force expressed through straw
> polls in New Orleans is a problem. In fact, I would characterize the actions
> we took in New Orleans to be an example of group think gone wild.  We had a
> comprehensive SSTL specification in the draft, but made the straw poll votes
> to change on concepts, not proposed specifications.
> There is no standard for HSTL at 1.8 volts (the preferred voltage per straw
> poll), nor did the TF select any other parameters of the electrical
> specifications.  (Class I, 1.5 volt  HSTL as specified in EIA/JESD8-6 is the
> closest standardized alternative that the team working on clause 46 could
> find).  Because we couldn't find a standard to reference and the Task Force
> didn't endorse a complete set of 1.8 volt specifications, there was no way
> an HSTL electrical specification could be inserted into the draft without
> adding a lot of technical material that hadn't been endorsed by the
> committee.  Therefore, all you will find in Draft 1.1 on HSTL is an editor's
> note describing the situation.
> Most discussion supports the idea that the XGMII electrical interface is for
> near term usage (with continued use as an module to module logic interface
> within a chip). Implemeters expect the electrical interface to be supported
> by I/O devices in quick turn silicon libraries.  Some participants in the
> editorial session thought ASIC vendors might have a 1.8 volt HSTL derived
> from the above referenced specification, but weren't sure of any vendors
> supporting it (for inclusion in the standard it should be supported by many
> vendors).
> We have a similar problem with the clock alignment were the straw poll
> endorsed a change without any specifications to implement the change (e.g.,
> skew specifications).
> As it now stands, I would vote against going to Task Force ballot.  It would
> be a shame for TF ballot to be delayed because of the absence of XGMII
> electricals.  I see three alternatives that would allow us to go forward to
> TF ballot.
> 1.  Return to the SSTL specifications of Draft 1.0
> 2.  Reference HSTL at 1.5 volts per EIA/JESD8-6 and select from the options
> within that specification.
> 3.  Someone presents a detailed proposal including all appropriate
> specifications (timing, thresholds, AC and DC characteristics, termination,
> etc.)
> As the clause editor, I will be proposing alternative 1 in Tampa unless
> participants come through with presentations (sufficiently detailed to go to
> TF ballot), and the Task Force endorses the specifications presented.
> Bob Grow
> Editor Clause 46