Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

Re: XGMII electricals -> MDIO electricals

Hi Ed,

I also have concerns about these levels.  The present clauses in 802.3
that describe these levels allow voltages well above 5V, but I don't
know of any 1.8V devices whose MDC/MDIO ports can withstand this
without blowing a hole in the oxide.  There needs to be some way to
allow alternate voltages for this interface and still be standards


Ed Grivna
Cypress Semiconductor

> Jeff,
> I'd like to pick up your last point : "...what about MDC/MDIO levels?".
> For D1.1 I inserted an editors note under an "Electrical interface" section as 
> place holder for an interface to be approved by the Task Force.  At the Tampa
> meeting I intend to propose that we just adopt the logic family that the XGMII
> uses (we might have to put a note in about termination schemes as the MDIO is
> multi-drop).
> If anyone has any specific concerns with this I encourage them to voice them 
> bring bring forward an alternative proposal to the meeting.
> Regards
> Ed
> "Jeff Porter (rgbn10)" <j.porter@xxxxxxxxxxxx> on 02/11/2000 22:18:44
> Sent by:  "Jeff Porter (rgbn10)" <j.porter@xxxxxxxxxxxx>
> To:
> cc:   "'stds-802-3-hssg'" <stds-802-3-hssg@xxxxxxxx> (Edward
>       Turner/GB/3Com)
> Subject:  Re: XGMII electricals
> In an effort to get us all on the same page, here are links to
> the standard XGMII interface proposals, SSTL-2 and HSTL Class 1
> on the JEDEC site under "Free Standards":
> HSTL Class 1
> SSTL_2 Class 1 (per page 9,
> First, I also discourage the development of a new 1.8V interface definition
> for XGMII for many of the reasons already on the reflector.
> I regret not making a larger issue in New Orleans about the fact
> that HSTL is a 1.5V specification.  I thought there was consensus on
> the idea of saving power by going to HSTL, and was (too) willing to
> go along with voting on HSTL and 1.8V at the same time based on
> claims that there was another standard out there, and assuming that
> lacking a standard, we would still go to real (1.5V) HSTL.
> The very valid point has been made that interface variations outside
> of the IEEE standard often become popular, and that may also
> become true with XGMII.  So the question is where the standard
> should point, what guidance should we give implementers?  Since HSTL is
> available, standardized, and lower power, this makes a better *standard*
> interface than SSTL_2 (similar attributes, but higher power).
> That is, guide implementers toward a lower power solution.
> It has been stated that 2.5V SSTL_2 interfaces are implemented on
> early XGMII interfaces.  There was discussion at New Orleans that at
> least some of these interfaces also work down to 1.8V. Even if we select HSTL
> (i.e. 1.5V), as a practical matter, many 0.18um HSTL interfaces may also work
> up to 1.8V, which may be more convenient in systems at first than a 1.5V 
> If XGMII lives long enough for some reason, the market might go to even lower
> "1.5V tolerant" interface (e.g. 0.9-1.6V range specified in jesd8-11.pdf,
> October 2000, but with 50 ohm drive level).
> Perhaps a bigger question is, what about MDC/MDIO levels?
> Jeff
> "Grow, Bob" wrote:
> >
> > Implementing the XGMII concensus of the Task Force expressed through straw
> > polls in New Orleans is a problem. In fact, I would characterize the actions
> > we took in New Orleans to be an example of group think gone wild.  We had a
> > comprehensive SSTL specification in the draft, but made the straw poll votes
> > to change on concepts, not proposed specifications.
> >
> > There is no standard for HSTL at 1.8 volts (the preferred voltage per straw
> > poll), nor did the TF select any other parameters of the electrical
> > specifications.  (Class I, 1.5 volt  HSTL as specified in EIA/JESD8-6 is the
> > closest standardized alternative that the team working on clause 46 could
> > find).  Because we couldn't find a standard to reference and the Task Force
> > didn't endorse a complete set of 1.8 volt specifications, there was no way
> > an HSTL electrical specification could be inserted into the draft without
> > adding a lot of technical material that hadn't been endorsed by the
> > committee.  Therefore, all you will find in Draft 1.1 on HSTL is an editor's
> > note describing the situation.
> >
> > Most discussion supports the idea that the XGMII electrical interface is for
> > near term usage (with continued use as an module to module logic interface
> > within a chip). Implemeters expect the electrical interface to be supported
> > by I/O devices in quick turn silicon libraries.  Some participants in the
> > editorial session thought ASIC vendors might have a 1.8 volt HSTL derived
> > from the above referenced specification, but weren't sure of any vendors
> > supporting it (for inclusion in the standard it should be supported by many
> > vendors).
> >
> > We have a similar problem with the clock alignment were the straw poll
> > endorsed a change without any specifications to implement the change (e.g.,
> > skew specifications).
> >
> > As it now stands, I would vote against going to Task Force ballot.  It would
> > be a shame for TF ballot to be delayed because of the absence of XGMII
> > electricals.  I see three alternatives that would allow us to go forward to
> > TF ballot.
> >
> > 1.  Return to the SSTL specifications of Draft 1.0
> > 2.  Reference HSTL at 1.5 volts per EIA/JESD8-6 and select from the options
> > within that specification.
> > 3.  Someone presents a detailed proposal including all appropriate
> > specifications (timing, thresholds, AC and DC characteristics, termination,
> > etc.)
> >
> > As the clause editor, I will be proposing alternative 1 in Tampa unless
> > participants come through with presentations (sufficiently detailed to go to
> > TF ballot), and the Task Force endorses the specifications presented.
> >
> > Bob Grow
> > Editor Clause 46