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RE: Clarification on added B2/B3 bytes in WIS

Title: RE: Clarification on added B2/B3 bytes in WIS


A) Your understanding of the B2's is correct.

B) The 4x DPRAM approach was suggested by Pankaj Kumar.
   Here's his explanation from a previous e-mail:

    "In the transmit direction , one dual port RAM  192 X 8 will be required
for partial calculation and 192 X 8 for store to insert into the outgoing
  Also in the receive direction, one dual port RAM of 192 X8 will be
required for partial calculation and another 192 X8 Dual port will be
required for Storing and comparison
for B2 error count.
So total number of Dual Port RAMs will be 4 for both transmit and receive
direction. They will be running at 77.76 MHz.
    B2 Calculation could be performed at STS-12/STM-4 where the data bus is
8-bit wide running at 78 MHz. The size of the DPRAMs will be 12X8 . This
structure of the
DPRAM will be used 16 time ( STS-12 X 16 ).
    In the technology of 0.25,0.18 micron , This circuit is feasible using
Dual port Rams."

C) Note the B3 byte was not an addition, it was already in D1.0.
   Your understanding of the B3 mechanism is correct.


David W. Martin
Nortel Networks
+1 613 765-2901  
dwmartin@xxxxxxxxxxxxxxxxxx <mailto:dwmartin@xxxxxxxxxxxxxxxxxx>


-----Original Message-----
From: Gordon Jacobs [mailto:jac@xxxxxxxxxxxxxxx]
Sent: Monday, November 13, 2000 3:58 PM
To: stds-802-3-hssg@xxxxxxxx
Cc: jac@xxxxxxxxxxxxxxx
Subject: Clarification on added B2/B3 bytes in WIS

  I would like to confirm my understanding of the B2 parity bytes
added in the WIS overhead as per the motions in Tampa last week.
Looking at SONET descriptions, each of the 192 B2 bytes represents
the BIP parity of each of the 192 ST1s in the last frame, but
Section Overhead is excluded, and parity is calculated before
scrambling. As such the B2 parity bytes meet the following rules:

1. exclude columns 1,2,3 and include columns 4-90 in rows 1,2,3
  (i.e. excludessection overhead)
2. include columns 1-90 in rows 4-9, and as such,
  includes the B2 byte from the last frame, in row 5, col 1.
3. includes the path overhead (first B2) and fixed stuff
  (next 63 B2s) in the calculation for the SPE.


Since the B2 bytes represent the BIP parity for the last frame,
there is 2x storage required for the history mechanism. Why does
show four 192x8 RAMS for hardware requirments to generate
the B2 bytes rather than two 192x8 RAMS (current frame and
last frame)?

Finally, for the B3 parity byte, ANSI T1.105-1995 states that
the B3 calculation excludes the fixed stuff bytes. For the WIS,
there are 63 bytes of fixed stuff after each path overhead byte
which are zero. Obviously these can't affect the parity
calculation on Tx (since they are zero), but the ANSI doc implies
that they should be ignored in the receiver (i.e. a bit error in
the fixed stuff will not cause a B3 parity failure). Is this
Thank you very much,
Gordon Jacobs