Clause 48: Data Delay Estimation
I think that the the data delay estimation in section 22.214.171.124 is slightly
The maximal skew between lanes is said to be 85 bits (page 148 in D1.1). The
maximum delay estimation is 33.6n which is 105 UI. This leaves about 20 bit
delay for internal logic. If the architecture is based on 156.25Mhz clock,
any clock cycle is 20 bits. So you are left with only one extra sample!
Even for lower skew estimation, I think that a delay estimation should leave
a gauardband for couple of samples, typically about 4 samples due to logic
and circuit issues. 4 samples with 156.25 clock is additional 80 bits only
for implementation delay within the PCS.
So, I propose to increase the number by about 80 bits to something around
180 bits (about 60ns)