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This message for Justin Chang.
I see you have added a note in draft 2.0 pointing out that the value of TD - the variation of PMA_TXCLK_SRC to PMA_TXCLK delay - is possibly too large at 30ns. As we discussed at the Tampa meeting, I would still like to understand reason why TD was originally proposed to be as large as 30ns. TXCLK_SRC is used to clock the 16 bit parallel data out of the PCS, together with the TXCLK. It should be possible for this delay variation to be very small - a few ns at the most. I still believe that most Serdes vendors will have trouble meeting a value as large as 30ns. I am intending to propose a much smaller value in my ballot comment, but would appreciate some initial discussion too confirm the rationale. Would a conference call be valuable?