Question Regarding De-Skewing in Clause 48 (D2.0)
Something in "PCS de-skew state diagram" is not entirely understood:
When the machine transients from "ALIGN_ACQUIRED_1" to "ALIGN_ACQUIRED_2" it
goes to the state "BYTE_SLIP_WAIT" where it waits for one additional byte to
1) What is the motivation? Is it to prevent a split ||A|| column to be
counted as two errors instead of just one?
2) Why the machine does not transient through similar state while changing
states, for instance, from "ALIGN_ACQUIRED_2" to "ALIGN_ACQUIRED_3"
Thx. for your help,