FW: cls51 PCS output timing
On the PCS output it's not the 600ps board spec that's tight. It's the
1100ps PCS output spec.
As you point out, we want more setup/hold time for the PCS in the other
direction. Similarly we need to allow more slack to the PCS in the transmit
I would like to get numbers from some board/connector people. I don't think
they need 500ps-600ps.
From: Jscquake@xxxxxxx [mailto:Jscquake@xxxxxxx]
Sent: 7. december 2000 03:10
To: henning.lysdal@xxxxxxxxx; stuart_robinson@xxxxxxxxxxxxxxxx
Subject: Re: cls51 PCS output timing
Hello Henning, Stuart,
If the 600ps is tight then the return path PMA to PCS is even tighter. That
is spec'd with a 500ps margin ...
PMA output 1500-400=1100ps
PCS setup 600ps
total left for margin is 500ps
The point of the asymmetry was to give more setup and hold for the CMOS
PCS IC. I agree that we should hear from the system designers on this one.
The place where we could cut back are
1) setup and hold for the PMA input (better technologies) ... change to
2) setup and hold for PCS (overly generous w/ 300ps?) ... change to 200ps
as well ... this would make everything symmetric
Total budget in both directions would be 1550-800=750ps for the board
designer (connector and traces). Thoughts?
I think I would put this out on the reflector?
In a message dated 12/1/00 3:09:10 AM Pacific Standard Time,
> Our CMOS designers have informed me that the PCS output timing is pretty
> Looking at the numbers:
> Period approx. 1.5ns (LAN mode)
> PCS output data valid: 1100ps (1500ps - Tcq_min-Tcq-max, from table 51-3)
> PMA input valid requirement: 500ps (tsetup+thold, from table 51-4)
> Margin for board and connectors: 600ps
> I think we should get a realistic estimate from a system implementer on
> required margin for the board before we finalize these numbers. If not,
> end up putting tough restrictions on the PCS design for no appearant
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