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Clause 51: total delay variance spec

Reposting ... earlier try may not have gone onto reflector. See below.

Justin Chang
Quake Technologies, Inc.
50 Airport Parkway, San Jose, CA. 95110
Tel: 408-437-7723 email: justin@xxxxxxxxxxxxx
Fax: 408-437-4923 internet:

As of the last meeting there is still some question on the TD total delay
spec for the transmit clocks of the XSBI interrface. The initial spec for the
total delay variance (TD) number in Table 51-6. The present number of 30ns
seems excessive to some. I would like to put forth to all to state reasoning
to change or keep the number. For my position it is rather long. The suppose
history for this number is to accomodate a 15UI (644MHz --> 24ns) change. I
don't have clear support of this.

The intent of this spec is to allow for slow, low varying change due to
changes, baseline wander effects or other system changes that will cause a
change in the phase relation between the two clocks, PMA_TXCLK_SRC and
PMA_TX_CLK ... test frequency < 10KHz. From what I can gather in discussions
w/ a few people at the last two conferences, this number can be changed to
something less. I would like to propose something on the order of say 10ns
or less.