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Re: (Additional) Clause 51 Question


The difference here allows for different implementations.

If the duty cycle is poor, it may be better to compensate for the
time difference with board etch.

If the duty cycle is good or board skew is minimal, the inverted
clock can be used.

/Brian Cruikshank

James Colin wrote:
> Hi,
> I have a question about "PCS output timing" vs. "PMA
> Input timing": The tx_data-group is driven with the
> rising edge of the clock. Why cant the PMA sample it
> with the falling edge? The timing means that the clock
> and data must be rout with a different delay on the
> board in order to stand the specifications?
> Thanks,
> James
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