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Re: Question Regarding De-Skewing in Clause 48 (D2.0)


Answers below:

Boaz Shahar wrote:
> Rich,
> Something in "PCS de-skew state diagram" is not entirely understood:
> When the machine transients from "ALIGN_ACQUIRED_1" to "ALIGN_ACQUIRED_2" it
> goes to the state "BYTE_SLIP_WAIT" where it waits for one additional byte to
> be received.
> 1) What is the motivation? Is it to prevent a split ||A|| column to be
> counted as two errors instead of just one?

Yes. This is exactly the case.

> 2) Why the machine does not transient through similar state while changing
> states, for instance,  from "ALIGN_ACQUIRED_2" to "ALIGN_ACQUIRED_3"

It should. Don Alderrou of nSerial is submitting a comment to this
> Thx. for your help,
> Boaz


Best Regards,
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