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Re: MDIO register addresses

I have deliberately positioned the register bits and addresses so that the bits
appear in the same (or similar) locations down the stack of devices for a
particular implementation of a port type.
The example you gave of register 24 is a good one to highlight how this works.
You will see that any 10GBASE-4 implementation can always get it's lane status
from register 24, whether it's implemented as a discrete 10GBASE-X PCS or as a
re-timed XGXS.
Software engineers like this since once they have ascertained whether it's a
re-timed XGXS or discrete 10GBASE-X PCS then they don't need to worry about
which bits to poll for status - it's always register 24 bits 0-3. So long as
they are accessing the correct device, the routines can peek the same
bit/register locations. It could get very confusing if the lane status register
was in one location for one implementation and was in another location for
another implementation.
As the 10GBASE-W4 PMA is similar to an XGXS device (in that you have to report
status on four serial links) I put the status bits for the 10GBASE-W4 PMA in
register 24 as well.
The gapping of registers was required so I could line up this functionality
across the devices. In addition, I am expecting some additional common
functionality to be required on all devices and this will have to be put into
the gaps.


Clause 45 Editor.

Stephen.Finch@xxxxxx on 29/12/2000 17:33:35

Sent by:  Stephen.Finch@xxxxxx

To:   stds-802-3-hssg@xxxxxxxx
cc:    (Edward Turner/GB/3Com)
Subject:  MDIO register addresses

Curious as to how/why the registers numbers were selected.  At first I
thought they assigned unique register addresses to each register type
(e.g., "Status", "Control") regardless of the device type but a closer
look shows that this isn't true.  For example register address 24
contains 10GBASE-4 Status for a PMA/PMD device, 10GBASE-X PCS Status for
a PCS device, and Lane Status for XGXS devices.

Assuming that I haven't missed something, I suggest that we either
compress the register addresses for each device (eliminate reserved
registers from the middle) or make the register assignments unique for
all devices.


Steve Finch