RE: Clock Tolerance and WAN PHY
There is no intent or support for directly interfacing the WAN PHY to standard
SONET gear, especially in outside plant applications. Off hand, I can think of
the following obstacles, even if you did match the clocks:
- The optics are completely different
- Most of the overhead bytes are not supported (for instance, it
would not be possible to provision the ring)
- Much of the defects and alarm reporting is missing
While it is certainly possible for someone to put back the missing overhead
and defects and also use SONET optics rather than Ethernet optics, all this
is totally outside the scope of the 802.3ae standard.
From: James Colin [mailto:james_colin_j@xxxxxxxxx]
Sent: Sunday, January 21, 2001 12:54 AM
To: Luigi.Ronchetti@xxxxxxxxxxxxxxxx; tripathi@xxxxxxxxxxxx
Subject: Clock Tolerance and WAN PHY
I think that the motto in the WAN PHY standard is the
introduction of a new framing scheme (As opposed to
POS), rather than being gluelessly connectable to the
SONET network. The WAN PHY is supposed to be connected
to a SONET LTE (ELTE) that is doing clock drift and
Even if the WAN PHY Clock requirements were identical
to those of SONET, I'm not sure if the ELTE is still
needed or the WAN PHY can be directly interface to the
SONET ring. Can anybody comment on that?
--- Luigi.Ronchetti@xxxxxxxxxxxxxxxx wrote:
> Hi Devendra and all,
> I think that is not enough to reduce the clock
> tolerance to 50ppm.
> As far as I know, ITU-T is going to approve
> (February 2001) a new
> recommendation (G.709) that defines OTN (Optical
> Transport Network).
> Future optical backbones over long distances will
> likely to be realized
> using G.709 and this will happen before 10 GbE final
> In G.709, among the others, a CBR10G client signal
> is defined as "a
> constant bit rate signal of 9953280 kbit/s +/-20
> ppm" (for example an
> OC-192/STM-64 signal and then, in principle, also a
> 10 GbE WAN signal).
> So, in my opinion, at least for a 10 GbE WAN signal,
> the clock
> tolerance should be 20ppm.
> Best regards,
> \/ Luigi Ronchetti
> A L C A T E L via Trento, 30 - 20059 Vimercate (MI)
> TND R&D phone: +39-039-686.4793 (Alcanet
> fax: +39-039-686.3590 (Alcanet
> > -----Original Message-----
> > From: tripathi@xxxxxxxxxxxx
> > Sent: Tuesday, January 09, 2001 10:50 PM
> > To: stds-802-3-hssg@xxxxxxxx
> > Cc: tripathi@xxxxxxxxxxxx
> > Subject: Clock tolerance
> > Hi,
> > Right now we are specifying the clock tolerance of
> 100 ppm. Currently
> > in-expensive
> > oscillators are available with tolerance value
> less than 50
> > ppm. Just like
> > we are moving
> > voltage levels, it is time we revise the tolerance
> value too.
> > The elastic
> > buffer
> > requirements get simplified by this assumption. I
> > that we reduce it
> > to 50 ppm.
> > Regards,
> > Devendra Tripathi
> > VidyaWeb, Inc
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