RE: Clock Tolerance and WAN PHY
you must also consider aging of the oscillator. This
might be corrected, by usually you don't have an
onsite intervention to do this. Therefore you have
to consider frequency deviation during the period
of time during which the equipment is said to be
in operation. 10 years seems to be a good value
De : owner-stds-802-3-hssg@xxxxxxxx
[mailto:owner-stds-802-3-hssg@xxxxxxxx]De la part de Curt Berg
Envoyé : dimanche 28 janvier 2001 07:07
À : 'rtaborek@xxxxxxxxxxxxx'; HSSG
Objet : RE: Clock Tolerance and WAN PHY
I agree with Rich,
When a vendor specifies x ppm for an oscillator,
most guarantee this within a very narrow band
of both usage (cap loading, etc), and operational parameters.
It can be really hard to build an actual system
that is within the limits of what the vendors
operating/testing spec is for the actual ppm rating.
So most companies do two things :
1) Purchase oscillators with much better ppm rating then
then the system that they offer.
2) Implement manufacturing test, that system frequency is
actually well within the guaranteed system ppm rating.
So just because you can purchase 20 ppm oscillator, doesn't
mean it will be easy to guarantee this at system level!
From: Rich Taborek [mailto:rtaborek@xxxxxxxxxxxxx]
Sent: Saturday, January 27, 2001 9:11 PM
Subject: Re: Clock Tolerance and WAN PHY
D2.0 includes 32 occurrences of ppm tied to line rate and zero
occurrences tied to oscillator frequency. The cost of keeping the line
rate at +/- 100 ppm already requires oscillators with significantly
better tolerances than +/- 100 ppm. Since Ethernet frame size has
remained constant over the range of 10M/100M/1G/10G also keeping the
line rate ppm at +/-100 yields a cost effective PHY design with no
impact on elasticity buffer design.
Devendra Tripathi wrote:
> I started the thread on a very simple note that it is time we reduce the
> clock tolerance
> to 50 ppm as it greatly helps in design of elasticity buffers at various
> clock change
> points. The cost of 50 ppm and 100 ppm ocsillators are almost same (I wish
> had numbers,
> may be some one can provide that). This is similar request to moving
> level to
> lower values to facilitiate higher density and faster designs.
> If some one could compare cost of even lower ppms and we find it OK, it
> be wise
> to change the requirement even to that. At least we do not have to worry
> about being
> compatible to 10/100/1000 on this one.
> Devendra Tripathi
> VidyaWeb, Inc
> 90 Great Oaks Blvd #206
> San Jose, Ca 95119
> Tel: (408)226-6800,
> Direct: (408)363-2375
> Fax: (408)226-6862
> -----Original Message-----
> From: owner-stds-802-3-hssg@xxxxxxxx
> [mailto:owner-stds-802-3-hssg@xxxxxxxx]On Behalf Of Jonathan Thatcher
> Sent: Saturday, January 27, 2001 5:43 PM
> To: stds-802-3-hssg@xxxxxxxx
> Subject: RE: Clock Tolerance and WAN PHY
> I enter here with great trepidation. I would like to offer a couple of
> thoughts, based on our current draft (I am intentionally calling this by
> number) and what I remember reading on the reflector.
> 1. A 20 ppm clock or any other ppm less than or equal to 100 ppm would be
> compliant with the standard and would interoperate with all compliant
> 2. I do not remember seeing any data regarding the cost ratio offered
> between a 20 ppm clock and a 100 ppm clock. ($$ not allowed in
> 3. I do not remember seeing any data regarding the volume ratio of WAN to
> LAN PHYs expected in the market place.
> 4. I do not remember seeing any data regarding the cost ratio of an ELTE
> that has to support input of 100 ppm clock rates as compared to one that
> to support 20 ppm (or other).
> 5. Based on 2, 3, 4, I cannot therefore make even the simplest calculation
> regarding a global optimization.
> 6. Based on 1, and 5, I don't see anything broken and I see no supporting
> evidence that a change is beneficial (or, would provide incentive for 75%
> the voters to change this specification).
> A. I don't see any reason why a LAN PHY can't source data at the OC-192
> and still be considered compliant to the standard and fully interoperable
> with other LAN PHYs.
> B. From an implementation standpoint, it is quite reasonable to think of
> building an ELTE with the defined WIS and use a LAN PHY as the connection
> between the Ethernet equipment and the ELTE running the mode specified
> in A.
> C. The equipment ELTE built in B could easily translate between the two
> clock domains (100 ppm and anything less than 100 ppm).
> D. All that I describe above, I believe, would be compliant to the
> IEEE 802.3ae draft standard.
> Therefore, what is the problem? It seems to me that any of you can
> whatever you want and still be okay. I don't think that I am hearing issue
> with our draft. I think that I am hearing implementation questions/issues.
> What am I missing?
Richard Taborek Sr. Phone: 408-845-6102
Chief Technology Officer Cell: 408-832-3957
nSerial Corporation Fax: 408-845-6114
2500-5 Augustine Dr. mailto:rtaborek@xxxxxxxxxxx
Santa Clara, CA 95054 http://www.nSerial.com