Re: Question on XSBI Tx Timing.
The XSBI interface was written leveraging from the work done in the OIF forum (reference document is OIF1999.102). Now, the reason why the transmit side has the falling edge centered in the data is as follows. Usually there is a final latching of the parallel data before it is sent. So this is done on one edge (e.g. rising)inside the chip and this edge is the one that is aligned to the data. Given that in the system one may have to phase shift the (traces, delays) clock it was also put in that the "inversion" to rising be done external to the IC. Again, this is coming legacy work. Now for system applications where the clocks are good and the clock/data skew is minimal, one can just switch the +/- lines coming out of the clock going into the receive side.
Hope this helps.
I have a question regarding the XSBI clock specifications in clause 51
of 802.3ae Draft 2.0.
Table 51-1, and text in subclause 51.3.1, state that both the XSBI
transmit and receive data are latched on the "rising" edge of their
respective clocks (PMA_TX_CLK<P> and PMA_RX_CLK<P>). Figures 51-5 and
51-7, which show the timing of the data capture on both the transmit and
receive interfaces, also show a data valid window centered on the
"rising" edge of the clocks.
However, figures 51-4, table 51-3, figure 51-6 and table 51-7 all show
the signals being launched with the data valid window centered on the
"falling" edge of the clocks and the data invalid period specified
around the rising edge. This appears inconsistent.
Any clarification as to what was intended here will be greatly
Thanks, & Best Regards,
Julio C. Hernandez