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RE: Clause 46 question


Our intent was that the clock increment at the RX_CLK edge rate. In other
words, it is counting the passage of 128 columns rather than 256 columns.


-----Original Message-----
From: Eric Lynskey [mailto:elynskey@xxxxxxxxxxx]
Sent: Wednesday, February 14, 2001 9:59 AM
To: stds-802-3-hssg@xxxxxxxx
Subject: Clause 46 question


Is the text in clause 46 correct when it says that 128 columns not
containing a Sequence ordered_set must be received to clear the link_fault
variable?  The state machine needs the col_cnt variable to increment to 128,
and this increments at RX_CLK rate.  My confusion is that RX_CLK is defined
as nominally 156.25 MHz.  However, RXD<31:0> is sampled on both the rising
and falling edges of RX_CLK.  This means that after 128 cycles of RX_CLK,
256 columns have been received.  So, the real question is does the RS need
to see 4 Sequence ordered_sets in 128 columns or 256 columns?  I believe
there may be some issues if the RS needs to see 4 ordered_sets in 128
columns when connected to an XGXS and XAUI on both ends.  Before I look into
this more deeply, I'd like to know whether it's supposed to be 128 or 256

Eric Lynskey
UNH InterOperability Lab