Re: XGMII Clock Duty Cycle
The driver tsetup and thold requirements already place a limit on the
duty cycle variation of the DDR clock output.
I think a separate duty cycle specification will be redundant and may
reduce flexibility in the transmitter output design.
Do you see a need for a separate duty cycle specification?
James Colin wrote:
> I searched carefully for XGMII Clock duty cycle in
> Clause 46 of D2.1, Nevertheless, I could not find
> anything. Can anyone help with this? What is the duty
> cycle of the XGMII DDR Clock?
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