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Re: XAUI SJ jitter test

To: "Rogers Shawn" <s-rogers@xxxxxx>
Subject: Re: XAUI SJ jitter test
From: "Tom Lindsay" <Tom.Lindsay@xxxxxxxxx>
Date: Tue, 06 Mar 2001 13:08:58 -0800
CC: HSSG <stds-802-3-hssg@xxxxxxxx>
Organization: Vixel Corp.
References: <5921D0EE2081D2118D0D0000F8CD148C0B944966@xxxxxxxxxxxxxxxxx>
Reply-To: Tom.Lindsay@xxxxxxxxx
Sender: owner-stds-802-3-hssg@xxxxxxxx

At Vixel, we use the HP71501C system, which can to to 20 MHz. The limitation is in the phase modulator. I'm not sure what the spec is for the pattern generator, but the clock input port has >1GHz of bandwidth from what I can see from running a random noise source through it.

Tom

"Rogers, Shawn" wrote:

Tom, I'm asking you this as I seem to recall from the Jan Interim you presented on the Annex 48A jitter test approach. If I am in error please forgive me. In D2.1, Clause 47, Page 285, Figure 47-8 shows Sinusoidal Jitter Tolerance Mask that requires 0.1UI SJ tolerance up to 20Mhz. Can you or anyone on the reflector describe how this limit can be tested. I am told that the HP 3G and 12G BERTs can only modulate up to 10Mhz.Regards,Shawn Rogers

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  - From: Rogers, Shawn

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