Re: MDIO Electricals
Thank you for contributing to the MDIO electrical discussion. I have embedded my
responses in with your original e-mail.
Bryan Yunker <byunker@xxxxxxxxxxxxx> on 01/03/2001 00:23:27
Sent by: Bryan Yunker <byunker@xxxxxxxxxxxxx>
Subject: MDIO Electricals
As one of the suppliers of PMDs we have been in a position to look at the
specs of a number of XGMII to XAUI, XAUI to 10 Serial, and XSBI to 10G
serial VLSI for incorporation into optical transceivers we are
considering/developing such as XGP and XSBI VSR. We have noted that most
XAUI VLSI refer CMOS I/O to 1.8V or 3.3V, often with 3.3V tolerance. Adding
circuitry in the PMD to down-regulate and translate from 3.3V or 1.8V to
lower I/O voltages will impose negative space, power and cost impacts that
will be passed to the end user (who expect ever cheaper PMDs).
Whilst this is true, not only do we need to support today's XAUI and PMD parts
we also need to support today's MACs (where the Clause 45 master will probably
be placed), PCS and WIS parts. In addition there seemed to be a consensus that
Clause 45 should be written with provision to support future devices on the same
MDIO bus in the way that Clause 22 has served us well over the past years. This
certainly seemed to be the consensus within the Clause 45 comment resolution
track at the last meeting. As I said in another e-mail, I believe that the
selection of an electrical specification for Clause 45 is a most difficult task
in particular in relation to selecting an approach that is acceptable today, but
will not become a burden to future implementations.
-There are a number of parameters listed in the Clause 45 Proforma
(220.127.116.11) which are not in the 45.4.1 table that should be picked up in the
This is an editorial issue that will be fixed.
-The Clause 45 Annex voltage translator circuit suggested for Clause 45 to
Clause 22 MDIO compatibility is likely to carry royalty issues with Philips
Patent # 5,689,196, and again, would impose an undesirable circuit expense
to the VLSI and/or PMD.
No comment. The Chair of 802.3 will comment on the discussion of patents in
another e-mail to the reflector.
-The D2.1 timing does not appear to recognize the drive current and
capacitive load issues with 32 devices on the bus, i.e. is a 10ns setup and
hold achievable with a fully loaded bus at full speed operation? If the VLSI
or PMD provide an internal weak pull-up, will 32 of these in parallel allow
proper bus pull down?
The setup and hold time of 10ns you refer to is the timing specification for the
STA, the management station. Taking these values into account translates into a
allowable rise time of 380ns within the minimum MDC cycle time of 400ns
(remember that the MDIO has a maximum clock speed of 2.5MHz). The other timing
parameter that needs to be taken into consideration in this case is the MMD
timing, it has a slightly tighter timing requirement on it of a clock to output
of 300ns. So I believe the question should be will a 300ns rise time be
achievable on a full loaded bus of 32 devices. As for the comment about a weak
pull-up in each PMD (I assume you are referring to MMD) that was not the intent,
the key is in the statement that 'a' weak pull up, that is only one per MDIO
bus. It should be possible for the Clause 45 electrical interface to support the
same number of devices on the bus as the Clause 22 interface (that is certainly
the intent). Remember that it will not be long before multiple MMDs are
integrated into a single device or even multiple ports are integrated into a
single device. When that happens, the bus loading will drop further.
-There is an implication that MDIO is a CMOS point to point interface, or an
open drain bus, and an Iol/Ioh of 100uA is inadequate for the latter. What
are the OEM MAC designers planning to drive? We have already discussed
system cards with OEMs planning four to eight XGPs per card.
The 100uA figure was taken direct from the JEDEC spec and will need to be
significantly increased. We'll review this at the meeting.
-The ideal PMD (XGP for example) would have one pair of MDIO pins, with
internal connections to the VLSI and to the microcontroller providing PMD
management(temperature ,etc.). How would the bus timing accommodate 16 PMDs
with two internal devices/stubs each?
An ideal PMD would limit it's load so as to maximise the number of other devices
allowed on the bus. However, there is no reson why you cannot implement the PHY
with two internal MDIO slaves.
-It is unlikely that commodity suppliers of microcontrollers and EEPROMs
will flock to a sub 1.8V bus, making the current spec an exclusively VLSI
play, and forcing the PMD management to another set of precious PMD conector
pins. (we are pushing to avoid this in the XGP MSA)
It was with this issue in mind that we modified the specification to accommodate
both a 'straight' 1.8V I/O cell as well as an open drain implementation. This
decision was made during the Clause 45 comment resolution track in January.
A possible path to harmony on all points would be to morph the MDIO
electrical/timing definition a "near" clone of the I2C bus with the
-the I2C electrical/timing definition does not appear to be covered by
Philips patents (SMBus cloned it)
-the I2C switching levels scale with VDD over the Clause 22 and 45 VDD
ranges(Maintaining Clause 22 compatibility)
Although I2C allows different voltage levels, it requires the use of translation
devices between the different voltage domains. We are proposing the same
approach for Clause 22 / Clause 45 compatibility.
-I2C now has a 3.4MHz mode (How does MDIO get to 25MHz with 32 devices
MDIO has a maximum speed of 2.5MHz. I2C will only support the 3.4MHz mode at a
bus load of 100pF. We intend to get the Clause 45 interface to support the same
number of devices that Clause 22 supported on a 470pF load bus.
-I2C preserves the legacy PMD management interface and OEM ASIC investments
-(GBIC is I2C, and a 1Gb 802.3 PMD after all...)
I2C has not previously formed part of the 802.3 management interface therefore
an I2C interface to the PMD has never been supported. We are providing support
of the legacy Clause 22 management interface through our careful selection of
-The I2C bus performance is well known and defined
-The PMD can adapt to the differing signaling protocols between I2C and
The proposed Clause 45 electrical interface is similar to I2C which also uses
open drain drivers and resistive pull ups. A PMD therefore could just as easily
adapt between low voltage I2C and Clause 45.
References to GBIC 5.5, PHY Management a.k.a Transceiver Management Services
(TMS)in the SFF group,Current I2C and SMBus specs, etc. are available at:
We hope this will spark a healthy discussion to the benefit of all.