RE: Implementation vs. Standard
Or in the immortal words of 802.3 (clause 1.2.1 and other places):
The models presented by state diagrams are intended as the primary
specifications of the functions to be provided. It is important to
distinguish, however, between a model and a real implementation. The models
are optimized for simplicity and clarity of presentation, while any
realistic implementation may place heavier emphasis on efficiency and
suitability to a particular implementation technology. It is the functional
behavior of any unit that must match the standard, not its internal
structure. The internal details of the model are
useful only to the extent that they specify the external behavior clearly
I don't know of any implementations that put the MAC state machine in real
From: Booth, Bradley [mailto:bradley.booth@xxxxxxxxx]
Sent: Tuesday, March 27, 2001 10:02 AM
Subject: RE: Implementation vs. Standard
If the circuit you design complies with the standard, how is anyone to know
how you implemented it? What matters is what it seen on the MDI. If that
looks correct, then you can implement it in FORTRAN for all I care.
From: Justin Gaither [mailto:jgaither@xxxxxxxxxxxxxxx]
Sent: Tuesday, March 27, 2001 10:59 AM
To: Taborek, Rich; 802.3ae
Subject: Implementation vs. Standard
<< File: Card for Justin Gaither >> Rich,
a while back I sent a message about PUDI(/INVALID/)
placement. In your reply you said:
Rich Taborek wrote:
> The Sync state machine is written to operate in the 10B
domain as is the
> Deskew state machine.
> The 10GBASE-X PCS does not mandate the location and number
> in an implementation. The PCS Sync and Receive state
> is virtually identical to that of the 1000BASE-X PHY. The
> function can be located elsewhere, but I don't view such a
> being more or less "correct" than it's current location.
> As to your second point, Invalid represent a superset of
> code-groups and running disparity errors. Therefore,
> error is not a suitable replacement for Invalid.
> Best Regards,
I am new to the standards based design, so I dont quite
the line between standard and implementation is drawn.
It was my understanding from the spec. that the "PCS shall
Transmit process as depicted in Figure 48..., including
the associated state variables as specified in 48..."
means, I have to
put the decoder where specified, and not before the deskew
state machines. Now I know I could design a circuit that
same as the standard but place the decoder before the deskew
but is this still compliant? Can I still select Yes in the
meeting the requirements of the State Machines?
Justin Gaither Phone: 512-306-7292
RocketChips a Division of Xilinx Fax: 512-306-7293
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