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RE: Clause 48 Questions


There is a difference between the delay specified in prior drafts which was
for MDI to XGMII and the delay specified here which is only the delay of a
single PCS or a single XGXS. The old delay therefore included the PMD delay
which now has a separate 512 bits round trip allocated. The editiors were
tasked to come up with reasonable delay figures and a consistant way to
express them for all the sublayers. The new number appeared in clause 44 of
D2.1 in a table summarizing all the delays but clause 48 was not updated to
match. This of course resulted in comments and the change you see in D2.3
reflects the resolution of the comments.

On your second point, the rules for error propagation never require an error
to be moved back 2 columns. They only require an error in the |T| column
that falls after the /T/ to be copied  to the prior column and an error in
the column after the |T| column to be copied to the |T| column. Therefore,
the error propogation rules require an additional delay of 32 BT. (Remember
that BT is bit times for the MAC bits - a column has 32 MAC data bits
encoded into 40 code bits.)

On your third question, I think you have found a mistake. The delay in
clause 48 should include the PMA. That is what the entry in Clause 44


-----Original Message-----
From: Boaz Shahar [mailto:boazs@xxxxxxxxxxxx]
Sent: Tuesday, March 27, 2001 8:02 AM
To: HSSG (E-mail)
Subject: Clause 48 Questions

Couple of  questions occurred to me while reading D2.3:

1) In previous drafts (I think it was D2.1), the specified delay from Start
sampling to MDI output is 1024BT, and the delay from MDI input to XGMII
Start is 1024BT as well (Table 48-6, D2.1). 

In D2.3 the table is missing, and the text says that the sum of the above
delays is 1024BT. This means about half the delay for the receive and the
transmit. Is that the intention? And if so: What is the reason for the big

2) Referring the recent discussion about propagating the error after the
packet to within packet boundary: This requires two additional samples of
the data, because sometimes you have to generate error in a column that was
there two clocks before. This increases the delay at least in two samples in
each lane, or 8 data bytes, or 80 BT?

3)What is the delay constraint for the PMA of 10GBASE-X?