RE: Implementation vs. Standard
The Synchronization state diagram checks for conditions like /COMMA/ and
/INVALID/, etc. to move between it's states. All state transitions must be
implemented in order to be compliant with the standard. The Synchronization
state machine does not require nor preclude a full decoder to check for the
I can't tell you whether your specific circuit/implementation is compliant
with the standard or not based on your placement of "the decoder". That's
not enough information. You can only select [YES] in the corresponding PICS
entry if compliance with the PICS entry, in this case the Synchronization
state diagram and all its state variables is met. If you're implying the
latter by saying that your circuit "behaves the same as the standard" then I
believe that you can set the corresponding PICS entry to [YES].
Richard Taborek Sr. XAUI Sherpa Intel Corporation
Santa Clara Design Center Network Components Division
408-496-3423 Fax: 408-486-9859 Cell: 408-832-3957
3101 Jay Street, Suite 110 Santa Clara, CA 95054
> -----Original Message-----
> From: Justin Gaither [mailto:jgaither@xxxxxxxxxxxxxxx]
> Sent: Tuesday, March 27, 2001 8:59 AM
> To: Taborek, Rich; 802.3ae
> Subject: Implementation vs. Standard
> a while back I sent a message about PUDI(/INVALID/) and decoder
> placement. In your reply you said:
> Rich Taborek wrote:
> > Justin,
> > The Sync state machine is written to operate in the 10B
> > domain as is the Deskew state machine.
> > The 10GBASE-X PCS does not mandate the location and number
> > of decoders in an implementation. The PCS Sync and Receive state
> > machine structure is virtually identical to that of the 1000BASE-X
> > PHY. The DECODE function can be located elsewhere, but I don't
> > view such a change as being more or less "correct" than it's
> > current location.
> > As to your second point, Invalid represent a superset of invalid
> > code-groups and running disparity errors. Therefore, running
> > disparity error is not a suitable replacement for Invalid.
> > Best Regards,
> > Rich
> I am new to the standards based design, so I dont quite
> understand where the line between standard and implementation
> is drawn.
> It was my understanding from the spec. that the "PCS shall
> implement its Transmit process as depicted in Figure 48...,
> including compliance with the associated state variables as
> specified in 48..." means, I have to put the decoder where
> specified, and not before the deskew and sync state machines.
> Now I know I could design a circuit that behaves the same as the
> standard but place the decoder before the deskew and sync, but
> is this still compliant? Can I still select Yes in the PICS to
> meeting the requirements of the State Machines?
> Justin Gaither Phone: 512-306-7292 x529
> RocketChips a Division of Xilinx Fax: 512-306-7293
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> Bldg 3 email: jgaither@xxxxxxxxxxxxxxx
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