Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

RE: Clause 44 Question




Boaz,

Yes, it is there for flow control or pause capabilities.  This information
is consistent with what was provided for in previous versions of 802.3.

If you feel that the numbers should be adjusted, then please submit a
comment against the draft with a suggested remedy.

Thanks,
Brad

	-----Original Message-----
	From:	Boaz Shahar [mailto:boazs@xxxxxxxxxxxx]
	Sent:	Thursday, March 29, 2001 6:43 AM
	To:	HSSG (E-mail)
	Subject:	Clause 44 Question


	Hi,
	Regarding the "delay constraints" in Chapter 44:

	What is the reason for the delay requirements? Is it just the size
of the
	buffer that is required in the MAC for the implementation of the
PAUSE
	protocol? According to table 44-3 (D2.3), even  the delay of a fiber
as
	short as 1km is about 80K bit. And probably many applications will
have much
	longer fiber path.

	For instance, the delay of the XGXS is 1K bit, for Tx+Rx. Assuming
512 bits
	for Rx, this is 128 bit / channel, or 16 bytes, from PMA to XGMII.
As max
	skew is 41 bits, a deskewing FIFO has a depth of more then 4, say 5
Bytes.
	The PMA itself has 1-2 samples. Additional gap must be provided for
clock
	tolerance, creating additional, say, two samples. The "Copy back" /
"Push
	back" function requires at least additional one. Now if the
implementation
	is with 312.5Mhz clock, it seems fine. However, if we do not want to
force
	the user to do it with such fast clock, then with 156.25 Clock any
sample
	means 16 bits, or 2 bytes, and we are out of budget. And there are
more
	things to do: State Machines, 8B/10B etc.

	I think that in this frequency it is somewhat problematic
constraint, and in
	order to enable more implementation options, should be enlarged
(Easier to
	implement). Especially if one needs a x100 times bigger buffer
because of
	MDI delay anyway. 


	Boaz