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RE: One common type of 64B/66B PCS?

I am not in favor of going to one clock rate. The ability of one 10GBASE-R
link to carry traffic aggregated from 10 1000BASE-X links is very important
in some applications. We went to some trouble with the start delimeter
alignment issue to ensure that the requirement to align start delimiters to
4 byte boundaries didn't decrease the link throughput. That throughput
reduction would have been about 3% in the extreme case where every packet
was a 65 byte packet and much less with a normal packet mix. I don't think
people are ready to give up more than 5% of their throughput in the LAN
I'm concerned that we are past new feature cut-off. If that weren't the case
or this wasn't considered a significant new feature, I would be in support
of adding something to say that a node which can operate in both modes and
parallel-detect should default its transmitter to the LAN mode. One would
have to check the PCS MDIO bits to make sure they supported that.
-----Original Message-----
From: Tim Warland [mailto:twarland@xxxxxxxxxxxxxxxxxx]
Sent: Tuesday, May 01, 2001 6:26 AM
To: pat_thaler@xxxxxxxxxxx
Cc: Luigi.Ronchetti@xxxxxxxxxx; Paul Bottorff; stds-802-3-hssg@xxxxxxxx
Subject: Re: One common type of 64B/66B PCS?

pat_thaler@xxxxxxxxxxx wrote: 


As long as the receiver's PLL has enough range to lock onto either clock 
rate, then parallel detection has no need for 10GBASE-R and 10GBASE-W to 
have the same clock rate. An auto-detect capability between 10GBASE-R and 
10GBASE-W requires only one thing that isn't in the current standard: 
agreement on what the default should be when two dual capability nodes are 

I believe the proposal is for one clock (or line) rate at 9.95328Gbps. This
the PLL and the requirements for a reference oscillator. Only the ethernet
rate is different as described below. 

My vote is for a default to LAN mode. In the case where  SONET transport 
is used, the capability mode would be set (by an ELTE or similar) to WAN 
mode. This maximizes the potential data rate between two auto-detect capable


If one can agree upon that, then there isn't any ping-ponging, one doesn't 
need to agree on any time-outs, etc. It is all very simple.

Does this mean you are in favour? 

> >Consider to have only one type of PCS that can remove (add) idles as 
> >for WIS applications and can integrate (as option) the SONET framer: 
> >the upper interface of this PCS may connect to the RS through the 
> >XGMII or this PCS may connect to an XGXS sublayer. 
> >The XGXS and the RS provide the same service interface to this PCS. 
> >The lower interface of this PCS connects only to the PMA sublayer 
> >to support the same PMD. 
> > 
> >When the SONET framer inside this PCS is bypassed (or it is not 
> >present), the nominal rate of the PMA service interface is 622.08 
> >Mtransfers/s which provides capacity for the MAC data rate of about 
> >9.65 Gb/s. 
> > 
> >When the SONET framer inside this PCS is used, the nominal rate of 
> >the PMA service interface is again 622.08 Mtransfers/s which instead 
> >provides capacity for the MAC data rate of about 9.29 Gb/s. 
> > 
> >In both cases the MAC uses IFS stretch mode to ensure that there 
> >will be enough idle time that the PCS can delete idles to adjust to 
> >the lower rate, with two different values for ifsStretchRatio (about 
> >221 bits instead of 104 bits for the first case). 
> > 
> >Since the data rates are now the same and there is only one PMA 
> >interface connection, there are no more additional constraints. 
> > 
> >Here a list of Con's and Pro's (for sure it is not exhaustive): 
> > 
> >---- Con's ---- 
> >1) the LAN "useful" bit rate for 10GBASE-R is reduced by 3.5% 
> >2) need to introduce a new ifsStretchRatio value for that 
> >3) ... 
> > 
> >++++ Pro's ++++ 
> >1) only one type of 64B/66B PCS is needed (two ASICs with the same 
> >    pinout, one with, the other without the SONET framer, can be 
> >    hosted by the same PCB) 
> >2) only one type of REFCLK (622.08MHz) for serial PMA is needed 
> >3) PMA REFCLK is always independent from XGMII_TX clock 
> >4) PMA and PMD, just characterized for SONET, can be used without 
> >    the need of further investigations/tests (for example the 
> >    10Gig MSA module or an OIF defined VSR can be used for both 
> >    LAN/WAN application) 
> >5) there is now the possibility to have an automatic adaptation of 
> >    the 10GbE interface to LAN or WAN applications, depending on 
> >    what is in between the two peer interfaces, or by presetting 
> >    (for an PCS with SONET framer inside, of course). 
> > 
> >  As a consequence there will be only 4 physical types instead of 7 
> > 
> >6) proprietary WDM solutions are able to better transport both LAN 
> >    and WAN signals because of 3R regeneration is now allowed, 
> >   (reclocking with a "standard" SONET clock is now possible) 
> > 
> >... and if, because of points 2) and 3), the PMA REFCLK is generated 
> >locally with an accuracy of at least 20ppm ... 
> > 
> >7) no synchronization problems (PJC thresholds reached) will be 
> >    reported when 10GbE WAN is transported over an SONET network 
> >8) the emerging OTN is now able to transport both 10GbE LAN and WAN 
> >    signals without the need of "special" adaptation


Tim Warland     P.Eng.

Hardware Design Engineer  Broadband Products

High Performance Optical Component Solutions

Nortel Networks                (613)765-6634