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RE: Serial PMA reference clock?


Ben is correct. Clause 49 leaves to the 10GBASE-R implementation the choice
of how to generate the transmit clock. (This is true of clause 48
10GBASE-X.) When there is no XSBI, the clock generation is controlled by the
requirement to meet the signal specs at the MDI. When there is an XSBI, the
requirements on PMA_TX_CLK must be met.

Since there is no compatability interface between the PCS and the WIS, how
to generate the clock and where to put the clock domain boundaries within
those sublayers is an implementation decision as well.


-----Original Message-----
From: Ben Brown [mailto:bbrown@xxxxxxxx]


I think this is an implementation issue. One implementation
may use a modified version of the XGMII TX_CLK as the PMA
reference clock. Another might choose to perform idle
insertion and deletion in the PCS to compensate for clock
differences between TX_CLK and the PMA reference clock.
Another might use a 66-bit internal serdes device and
would use a different means of converting from TX_CLK to
serial clock.

Putting something like this into the standard would imply
that one implementation is preferred over another. From
outside the device, any implementation is capable of
working and should be transparent to the test setup.


Justin Gaither wrote:
> Everyone,
>         What is the rate of the PMA reference clock?  Where does it come
> Is it locked to the same source as the MAC clock?
> I am assumeing the reference for the PMA is 644 or 322 Mhz, and that it
> is locked to the same source as the MAC XGMII TX clock.  So this would
> mean a frequency synthesizing PLL is required in the 10GBase-R PCS.
> Shouldnt we have specifications associated with this PLL?
> justin
> --
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