Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

RE: [802.3ae] Wan Interface Sublayer




Gerry,

I do not know how the clock tolerance change may have changed the jitter 
requirements.  I do not remember any change to the jitter specifications 
that were a result of the clock tolerance change.  Do you think that there 
should be?

Thank you,
Roy Bynum

At 08:29 AM 8/23/01 -0500, Gerry Pepenella wrote:
>Roy,
>         Does this apply to jitter requirements as well?
>
>Gerry Pepenella
>Silicon Laboratories
>
>-----Original Message-----
>From: owner-stds-802-3-hssg@xxxxxxxxxxxxxxxxxx
>[mailto:owner-stds-802-3-hssg@xxxxxxxxxxxxxxxxxx]On Behalf Of Roy Bynum
>Sent: Tuesday, August 21, 2001 11:42 PM
>To: Ayers, Mike; 'stds-802-3-hssg@xxxxxxxx'
>Subject: RE: [802.3ae] Wan Interface Sublayer
>
>
>
>Mike,
>
>As of Draft 3.1, the clock tolerances of the WAN PHY transmitter are the
>same as SONET and SDH Class B SRE and LRE receivers.
>
>Thank You,
>Roy Bynum
>
>At 04:16 PM 8/21/01 -0500, Ayers, Mike wrote:
>
>
> > > From: Roy Bynum [mailto:rabynum@xxxxxxxxxxxxxx]
> > > Sent: Monday, August 20, 2001 07:15 AM
> >
> > > As for being able to transparently carry 10GbE WAN PHY over
> > > an optical
> > > network, no additional systems other than what already exists in the
> > > service provider infrastructure is required.  Only if the WAN PHY is
> > > multiplexed into another transmission system other than 10G
> > > SONET or SDH is
> > > additional infrastructure needed, which is required regardless of the
> > > protocol or PHY.
> >
> >         So the clock and tolerances for WIS and SONET are the same.
> >Correct?
> >
> >
> >/|/|ike