RE: (3) [802.3ae] WIS Test Pattern Error Counts
I think you are right, and we have been at cross purposes. Sorry for
the inadvertent confusion. I think the issue here is the following sentence
in subclause 50.3.8:
"The test pattern checker shall have the ability to synchronize
to the mixed frequency test pattern and report bit errors detected
within the payload to the Station Management entity."
I intended this to mean that the test pattern checker would synchronize
to the TSS (which is a modified, but complete, SONET frame) and then
use the normal B1/B2/B3 BIP checks to detect and report errors. I now
see that it can also be interpreted in a wholly different way, namely that
the test pattern checker should synchronize to the PRBS pattern and report
specific bit errors in the PRBS pattern. This is clearly not the intended
result. I apologize for the long series of misunderstandings. In addition,
the phrase 'detected within the payload' is a leftover from the D3.1 version
of the test pattern mechanism, where there was indeed a requirement to
check the PRBS pattern and report errors. (This requirement was done
away with when warland_1_0701.pdf was used as a basis for the test
I think the wording should be changed to "The test pattern checker shall
have the ability to synchronize to the framed mixed frequency test pattern
as defined in 220.127.116.11.1, and report errors detected by means of the
normal BIP parity error checking mechanisms, using the B1, B2 and B3
octets within the frames." This should make it clear that the intent is to
synchronize to the TSS (defined in 18.104.22.168.1) and not the PRBS, and
to use the B1/B2/B3 facilities rather than some special payload bit error
checking. I can't talk about the "WIS frame" here, because the TSS is
actually a modified WIS frame, so I hope the reference to 22.214.171.124.1 will
clear things up for anyone who wants to know what a the framed mixed
frequency test pattern looks like.
If this makes things clearer I will see about putting in an official editorial
comment to fix up the text properly.
- Tom Alexander
From: Nepple, Bruce [mailto:bnepple@xxxxxxxxxxxxxxxxxxx]
Sent: Tuesday, September 18, 2001 12:40 PM
Subject: RE: (3) [802.3ae] WIS Test Pattern Error Counts
Now I am really confused. Sorry for being so thick headed.
It seems only logical that if the standard is going
to specify bit error checking functionality in addition
to the normal B1/B2/B3 parity checks, that it also
specify a means of reporting the results. It appears to
me that currently you require the bit checker functionality,
and the ability to report the results, but specify no method
to report the results.
The place where we may be confused may be at the definition
of bit error checking and reporting. The specification requires
that I synchronize, check, and report "bit errors", but only
supplies registers to report "bit lane parity errors". The other
point is that there is no need to synchronize to the received PRBS
data stream in order to detect and report B1/B2/B3 errors.
There are two types of synchronization. Synchronization to the
WIS frame, and synchronization to the PRBS sequence in the
SPE. The latter is not necessary to calculate B1/B2/B3 errors,
yet is required by the specification.
If the requirement was "to synchronize to the WIS frame and report
BIP parity errors (B1/B2/B3) within the frame", then the existing
register set would be adequate, and there would be no confusion.
> -----Original Message-----
> From: Tom Alexander [mailto:Tom_Alexander@xxxxxxxxxxxxxx]
> Sent: Monday, September 17, 2001 5:44 PM
> To: Nepple, Bruce; stds-802-3-hssg@xxxxxxxx
> Subject: RE: (2) [802.3ae] WIS Test Pattern Error Counts
> The fact that the B1/B2/B3 error checking processes are used
> to report bit errors does not imply that a test pattern checker
> function is not required, or that the test pattern checker will
> not report bit errors. The WIS clause specifies functionality
> and not implementation. The test pattern checker functionality
> is required to be present, even though an actual implementation
> of the WIS would most probably just re-use all of the Receive
> datapath mechanisms needed for normal operation, and add simple
> CID pattern processing logic to this. In fact, the last paragraph
> plus the last Note in subclause 126.96.36.199 tries to bring this out.
> Hope this answers your question.
> Best regards,
> - Tom Alexander
> WIS Scribe
> -----Original Message-----
> From: Nepple, Bruce [mailto:bnepple@xxxxxxxxxxxxxxxxxxx]
> Sent: Monday, September 17, 2001 4:53 PM
> To: stds-802-3-hssg@xxxxxxxx
> Subject: RE:(2) [802.3ae] WIS Test Pattern Error Counts
> Just to be absolutely sure:
> Does that mean that the sentence in 50.3.8
> (requiring a test pattern checker
> to synchronize and report bit errors)
> will be removed from the spec?
> > -----Original Message-----
> > From: Tom Alexander [mailto:Tom_Alexander@xxxxxxxxxxxxxx]
> > Sent: Monday, September 17, 2001 11:42 AM
> > To: Nepple, Bruce; stds-802-3-hssg@xxxxxxxx
> > Subject: RE: [802.3ae] WIS Test Pattern Error Counts
> > Bruce,
> > Your interpretation of D3.2 is correct. As per the resolution to
> > Comment #53 against D3.1, the existing bit error mechanisms are to
> > be used to detect and report pattern bit errors, as specifically
> > stated in the comment resolution:
> > "...The method of measuring bit errors shall be to use the
> > current B1, B2 and B3 SONET parity checking mechanisms in
> > the WIS Receive process. No additional logic shall be added
> > to the error checker for counting errors."
> > There is no Path Bit Error mechanism or counter in the normal WIS
> > processing, and therefore there is no Path Bit Error counter for
> > test pattern mode, either in Clause 50 or Clause 45.
> > There was an extensive discussion on this subject during the
> > comment resolution meeting. The general consensus was that the
> > existing B1/B2/B3 parity checks provided sufficient capability
> > for detecting test pattern bit errors, and also for providing
> > a rough assessment of the bit error rate. The view was that there
> > was no good reason to increase the WIS complexity by providing
> > additional hardware to measure the bit error rate more precisely.
> > I hope this answers your question.
> > Best regards,
> > - Tom Alexander
> > WIS Scribe
> > -----Original Message-----
> > From: Nepple, Bruce [mailto:bnepple@xxxxxxxxxxxxxxxxxxx]
> > Sent: Friday, September 14, 2001 7:26 PM
> > To: stds-802-3-hssg@xxxxxxxx
> > Subject: [802.3ae] WIS Test Pattern Error Counts
> > In 50.3.8 of D3.2 it is indicated that the WIS test pattern checker
> > shall have the ability to synchronize to the mixed frequency
> > test pattern and report bit errors detected within the payload
> > to the Station Management entity. It then goes on to describe
> > the Section BIP, Line BIP, and Path Block error counters, but
> > makes no mention of a Path Bit Error Counter. Did I miss
> > something? The three counters mentioned above will function
> > without a bit checker through the standard parity bytes.
> > I didn't see such a counter in 45.2.2 either.
> > Thanks
> > Bruce