RE: [802.3ae] Clarification request CJPAT etc
Clause 45 defines several pertinent bits relating to the selection and usage
of Clause 48 test patterns. Bit 5.24.11 indicates that the DTE XGXS is able
to generate test patterns. Bit 5.25.2 allows for the test pattern to be
transmitted when it is set to 1, and for the pattern not to be transmitted
when set to 0. Bits 5.25.1 and 5.25.0 allow you to select which test
pattern you want to use. Notice that you are allowed to select the Low
frequency, high frequency, and mixed frequency test patterns here. It is
correct that the ability to transmit these patterns is optional. If a
vendor chooses to implement internal pattern generators for these patterns,
then they need to use the proper register bits mentioned above. Please
note that all three of these test patterns may be transmitted directly
through the XGMII interface with D21.5, K28.7, and K28.5 for the high, low,
and mixed patterns, respectively.
I believe that the intent here was to allow some implementers to put
internal traffic generators on their chips to create the jitter test
patterns, and for some to use an XGMII or equivalent interface to create the
patterns. If you are going to use internal pattern generators, then you can
select the patterns through the registers in Clause 45.
The PICS statement in Clause 48 is specifying that you need to use the
patterns specified in Annex 48A to do jitter testing, and in particular, you
need to use CJPAT for receive jitter compliance testing. The reason for
this is that Annex 48A is specified as a normative annex.
Any further input is welcome, and please let me know if I'm way off base
[mailto:owner-stds-802-3-hssg@xxxxxxxxxxxxxxxxxx]On Behalf Of Tim
Sent: Thursday, October 25, 2001 9:05 PM
Subject: [802.3ae] Clarification request CJPAT etc
I would like to clarify some discontinuities within the latest version
of the 10GE document with respect to the requirement to implement
the High Frequency, low frequency, CJPAT and CRPAT generators
Clause 45 Describes a test pattern enable bit in various registers which
reference clause 48A (the XAUI test pattern clause) For example see
In every case, the test pattern enable bit is defined using text which
includes "Pattern testing is optional..." This implies that pattern testing
using the patterns described by Annex 48A is strictly optional.
However, there are two sections in the document which contradict
this requirement. Clause 48 PICS section 188.8.131.52 has a requirement
defined as CC1 "Jitter test Patterns" referencing Annex 48A with
MANDATORY capability status.
Beyond this, most of the patterns defined in Annex 48A contain the
text "pattern is not intended for jitter compliance testing" with the
exception of paragraph 48A.5 which states "The following pattern is
intended for receive jitter compliance testing."
It is my understanding that the requirement to generate and detect the
patterns defined by Annex 48A would be strictly optional, yet the PICS
and paragraph 48A.5 appear to contradict this intention. Could somebody
please clarify this understanding prior to my submission of a comment
to resolve this.
Tim Warland P. Eng.
Quake Technologies (613)270-8113 ext 2311
Tough Times don't last, tough people do
TITLE:Interim 10GEC Manager
ADR;WORK;ENCODING=QUOTED-PRINTABLE:;;Jere Chase OE, Room 201=0D=0A24 Colovos Rd.=0D=0ADurham, NH 03824
LABEL;WORK;ENCODING=QUOTED-PRINTABLE:Jere Chase OE, Room 201=0D=0A24 Colovos Rd.=0D=0ADurham, NH 03824