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Re: [802.3ae] ask some questions....





Hi,

t wrote:
> 
> At First, I have to say sorry.
> I still have some questions and maybe my questions are a little big.
> Thanks for your answer.
> 
> 1. This standard specifies a family of  physical layer implementations
> include
>     10GBASE-R, 10GBASE-W, 10GBASE-X. What do "R","W", and "X" mean?
>     "W" refer to" WAN", right?

R - Serial (64B/65B)
W - WAN (64B/65B - SONET)
X - DWDM (8B/10B)

> 
> 2. The XAUI is a low pin count, "self-clocked" serial bus that is
> directly evolved from the
>     Gigabit Ethernet 1000BASE-X PHY.
>     what does "self-clocked" mean?  XAUI, its working frequency is
> 2.5Ghz, right?

Each XAUI lane operates at 3.125 Gbps (2.5 Gbps * 10/8) using 8B/10B
encoding. With this type of encoding, the clock and data are encoded
in the same stream.

> 
> 3.(1) Jitter test mode operates when the PCS is attached to a WIS or
> not?
>         It seems jitter test mode operates with or without the WIS, then
> what's the difference between
>         jitter test mode operates with or without the WIS? and when need
> to operate in jitter test mode?
>    (2) Besides, what are normal mode and  jitter test mode mean, their
> functions are?

Currently, there are jitter test modes defined for LAN, WAN and XAUI.
They are all somewhat different. Some are intended to be used in the
lab for device verification. Others are available to be used in the
field for link integrity and BER determinations. Normal mode would
be typical data transfer mode as opposed to the transfer of a
particular test pattern.

> 
> 4. In the 802.3ae spec(Draft3.0 March 2001), I have some prolems about
> the figure50-2,
>     Can you tell me what's the function of the following connections?
>     because I don't find the answer in the text.
>     (1)connection between "receive process block" and " transmit process
> block"
>     (2)connection between "receive process block" and "layer management"
> 
>     (3)connection between "Synchronization process block" and "layer
> management"

You should probably start looking at D3.3 as D3.0 is over 6 months old.
These connections show explicit or implicit information exchange
between these processes.

> 
> 5. In clause 50, chapter 50.3.2.1, the following sentence makes me so
> confuse.
>    " The J1 octet shall transport a 16-octet continously repeating Trace
> Massage that is formatted
>      as defined by Section 5 and Annex A of ANSI T1.269-2000"
>     I guess it means when  transmits consecutive WIS frames, the Trace
> Massage octet shall be placed in J1,
>    and transmits 16 times, after all the 16 octets have been transmitted
> in this way, transmit process repeats, right?
>     That is the length of Trace Message is 16 octets, and each J1 has  a
> fixed value, right?

The trace message is 16 bytes. It is sent 1 byte at a time in the
J1 location in each SONET frame. J1 is not a fixed value, it changes
based on the trace message.

> 
> 6.In clause 50, chapter 50.3.2.2, the following sentence makes me so
> confuse.
>    "The H1 and H2 pointer octets shall be set by the transmit process,
> in accordance with the
>      pointer mechanism defined by ANSI T1.416-1999, to indicate a
> constant pointer value of 522 decimal,
>     and shall also indicate a concatenated payload"
>    (1) Each of  H1 and H2 is  8 bits, how to  indicate a constant
> pointer value of 522 decimal ?
>    (2) and their function are "pointer" , what it mean?

A thorough reading of T1.416-1999 might be useful. H1 & H2 bytes
are concatenated to provide both a pointer to the SPE as well as
to describe the type of payload.

> 
> 7. In the 802.3ae spec(Draft3.0 March 2001), I have some prolems about
> the figure50-3,
>     Why need the process path(line) defects block,but don't need a "
> process section defects block" ,
>     and what are these blocks doing?

Now you've gone past my level of expertise. I'll pass this one
to someone with more SONET knowledge than me (it shouldn't take
much :)

Regards,
Ben

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