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Re: [802.3ae] A Questuin about D3.4/ 47, 48

What??? 8B/10B has a max run length of 5. This translates to a lowest
frequency component of 312.5 MHz. This is slightly higher than 22 KHz. 

The "slanted" portion of Figure 47-5 is the low frequency mask and
corresponds to the +/-100 ppm XAUI clock tolerance. At the really low
frequencies, I believe that the 8.5 UI corresponds to the number of bits
that would have to be buffered in the case that clock tolerance
compensation is performed for a packet length equivalent to 22 kHz. The
8.5 UI and the slanted line itself has no relevance if clock tolerance
compensation is not performed. The 8.5 UI is only relevant on a per lane
basis and has no significance lane to lane. Therefore, the 41 bit deskew
in Table 48-5 holds.
Best Regards,

Boaz Shahar wrote:
> In clause 47, and figure 47-5, the sinusoidal jitter is 8.5 UI in
> very low frequency (Interval [0,22Khz]). This means that there is additional
> skew of 8.5 UI between lanes in the XAUI. That is  included in Table 48-5
> (Skew Budget)? In other words, while doing de-skewing, one should consider
> 41+8.5 as the max deskew situation or just 41?
> Thx.,
> Boaz
Richard Taborek Sr.                     Intel Corporation
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