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Re: [802.3ae] A Questuin about D3.4/ 47, 48




Boaz,

Please review the jitter tolerance mask explanatory material in Annex G
of the Fibre Channel - Methodology for Jitter Specification. Here's the
link to that document:
ftp://ftp.t11.org/t11/member/fc/jitter_meth/99-151v2.pdf

All relatively low frequencies, jitter orders of magnitude above 22 kHz
is completely tracked out by the CDR unit associated with a XAUI
receiver on each lane independently. 

Best Regards,
Rich
     
--

Boaz Shahar wrote:
> 
> Rich,
> I do not think it has something to do with the 100ppm drift. Drift is
> frequency deviation between two different clock domains, while jitter is the
> deviation of a certain signal edge location from its nominal location,
> regardless its frequency or other clock domain frequency.
> 
> I think that the interpretation of jitter is that Jitter=The deviation of a
> certain bit edge from its nominal location. So, saying Jitter of 8.5 UI in
> frequency 0 is allowed, as in figure 47-5, is saying that a certain point
> may be misslocated by 8.5 UI. This can happen even with DRIFT=0.
> 
> For instance, suppose there is no skew at all, but lane 0 is jittering to
> the right by 4 bits, and lane 1 to the left by 4.5 bits, and this happens in
> jitter frequency=0, that is, in a very slow way. This implies that this
> situation is almost constant. So there is is a skew of 8.5 bits between lane
> 0 and lane 1 although if there was not any jitter, the skew would be 0.
> 
> Otherwise, can somebody explain the meaning of the Sinusoidal jitter mask in
> figure 47-5? What is happening there in the interval [0,22Khz]?
> 
> Boaz
> 
> > -----Original Message-----
> > From: Rich Taborek [mailto:rtaborek@xxxxxxxxxxxxx]
> > Sent: Thursday, November 29, 2001 3:46 AM
> > To: Boaz Shahar
> > Cc: HSSG (E-mail)
> > Subject: Re: [802.3ae] A Questuin about D3.4/ 47, 48
> >
> >
> > What??? 8B/10B has a max run length of 5. This translates to a lowest
> > frequency component of 312.5 MHz. This is slightly higher
> > than 22 KHz.
> >
> > The "slanted" portion of Figure 47-5 is the low frequency mask and
> > corresponds to the +/-100 ppm XAUI clock tolerance. At the really low
> > frequencies, I believe that the 8.5 UI corresponds to the
> > number of bits
> > that would have to be buffered in the case that clock tolerance
> > compensation is performed for a packet length equivalent to
> > 22 kHz. The
> > 8.5 UI and the slanted line itself has no relevance if clock tolerance
> > compensation is not performed. The 8.5 UI is only relevant on
> > a per lane
> > basis and has no significance lane to lane. Therefore, the 41
> > bit deskew
> > in Table 48-5 holds.
> >
> > Best Regards,
> > Rich
> >
> > --
> >
> > Boaz Shahar wrote:
> > >
> > > In clause 47, 47.3.4.6 and figure 47-5, the sinusoidal
> > jitter is 8.5 UI in
> > > very low frequency (Interval [0,22Khz]). This means that
> > there is additional
> > > skew of 8.5 UI between lanes in the XAUI. That is  included
> > in Table 48-5
> > > (Skew Budget)? In other words, while doing de-skewing, one
> > should consider
> > > 41+8.5 as the max deskew situation or just 41?
> > > Thx.,
> > > Boaz
                                 
---------------------------------------------------------
Richard Taborek Sr.                     Intel Corporation
XAUI Sherpa                    Intel Communications Group
3101 Jay Street, Suite 110        Optical Group Marketing
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Cell: 408-832-3957          mailto:rich.taborek@xxxxxxxxx
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