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[802.3ae] Clause 49 - 64b/66b Control Codes Mapping and Bit Order


I would appreciate your help to clarify a couple of 64b/66b coding
convention questions.  As I am referring to walker_1_700.pdf, and the
example in his email of re: 64B/66B Control Codes Mapping & Bit Order, dated

At the time, the discussion was around the swapping the order (LSB->MSB) of
7-bit 10GBASE-R control codes for tranmitted bit order.  Since then,
10GBASE-R O codes were introduced, which consist of only 4 bits.  My
questions are:

- Is the swapping of control codes are still at boundary of 7 bits as
described in walker_1_700.pdf?  Draft 4.0 seems to refer to this convention.
- For the O-codes, should the swapping occur at 4 bit boundary as in the
7-bit control codes, or otherwise?

For instant, two frames output from RS as followed:

// RS output (Input to 64b/66b encoder)

frame 1 - fd,1 fe,1 07,1 07,1 07,1 07,1 07,1 07,1    - T0 (EOP0) with error
byte in byte #1 location
frame 2 - 9c,1 00,0 00,0 00,0 5c,1 00,0 00,0 00,0   - Sequence Order set
followed by Signal order set

To be encoded by 64b/66b framer as:

// For frame 1, should the internal 66 frame prior to scrambler would be as
per walker_1_700.pdf?

   <--87--> <--1e-><--00--><--00--><--00--><--00--><--00--><--00--><--00->

// For frame 2, should the swapping occur at the O-codes 4 bits boundary as

   <--55--> <--00--> <--00--> <--00--> <0-><f-> <--00--> <--00--> <--00-->


// should the swapping occur at 8 bit boundary, as the two back-to-back O
codes treated as data?

   <--55--> <--00--> <--00--> <--00--> <f-><0-> <--00--> <--00--> <--00-->