[802.3ae] 10GBASE-X PCS; status register definition?
I'm looking for clarification on how the PMA/PMD management register
1.1.2, "Receive Link Status" should behave when the PHY instance is a
10GBASE-X PCS/PMA. The specification describes it thus:
220.127.116.11.2 Receive link status (1.1.2)
When read as a one, bit 1.1.2 indicates that the PMA is locked to the
received signal. When read as a zero, bit 1.1.2 indicates that the PMA
is not locked to the received signal. The receive link status bit shall
be implemented with latching low behavior as defined in the introductory
text of 45.2.
which I guess is aimed at the optional sync_err signal on the XSBI for
the clause 49 PCS and clause 51 PMA. Thing is, it's not explicitly
mapped to any similar signal (or should I say primitive) on the
10GBASE-X PCS/PMA boundary, nor is it stated how it should relate to the
state of PMA lock of each and any of the 4 PMA lanes.
Does the draft need to be refined at this point? Or am I just failing to
spot the reference?
/ /\/\ Gareth Edwards mailto:gareth.edwards@xxxxxxxxxx
\ \ / Design Engineer
/ / \ System Logic & Networking Phone: +44 131 666 2600 x234
\_\/\/ Xilinx Scotland Fax: +44 131 666 0222