RE: [802.3ae] Clause 49 - 64b/66b Control Codes Mapping and Bit Order
First I would like to clarify something. 10GBASE-R O codes are not a recent
addition - only the name is new. If you look at walker_1_700.pdf page 19,
you will see the fields marked x and y. These contain the O codes though he
didn't call them that.
Note that the bits aren't swapped - they have one order, LSB first. Swapping
only comes up because we people tend to have been trained to think MSB
The hardware isn't.
Figure 49-7 clearly shows the order of the fields in the packet payload.
All fields are sent LSB first, a rule that applies to bit transmission
through-out 802.3. This rule is shown for the data bytes in the transmission
It would be good to add an explicit statement that the bits of each field
are sent LSB first to probably at 126.96.36.199. I thought this was stated
explicitly, but I can't find a spot where it is. This will need to be a
recirculation ballot comment. (A bit of a problem since we didn't make any
changes and that passed through first ballot without any comments, but a
comment requesting an editorial clarification will be likely to get
From: Tuan Hoang [mailto:tuanh@xxxxxxxxxxxx]
Sent: Monday, January 21, 2002 11:58 AM
Subject: [802.3ae] Clause 49 - 64b/66b Control Codes Mapping and Bit
I would appreciate your help to clarify a couple of 64b/66b coding
convention questions. As I am referring to walker_1_700.pdf, and the
example in his email of re: 64B/66B Control Codes Mapping & Bit Order, dated
At the time, the discussion was around the swapping the order (LSB->MSB) of
7-bit 10GBASE-R control codes for tranmitted bit order. Since then,
10GBASE-R O codes were introduced, which consist of only 4 bits. My
- Is the swapping of control codes are still at boundary of 7 bits as
described in walker_1_700.pdf? Draft 4.0 seems to refer to this convention.
- For the O-codes, should the swapping occur at 4 bit boundary as in the
7-bit control codes, or otherwise?
For instant, two frames output from RS as followed:
// RS output (Input to 64b/66b encoder)
frame 1 - fd,1 fe,1 07,1 07,1 07,1 07,1 07,1 07,1 - T0 (EOP0) with error
byte in byte #1 location
frame 2 - 9c,1 00,0 00,0 00,0 5c,1 00,0 00,0 00,0 - Sequence Order set
followed by Signal order set
To be encoded by 64b/66b framer as:
// For frame 1, should the internal 66 frame prior to scrambler would be as
// For frame 2, should the swapping occur at the O-codes 4 bits boundary as
<--55--> <--00--> <--00--> <--00--> <0-><f-> <--00--> <--00--> <--00-->
// should the swapping occur at 8 bit boundary, as the two back-to-back O
codes treated as data?
<--55--> <--00--> <--00--> <--00--> <f-><0-> <--00--> <--00--> <--00-->