RE: [802.3ae] XSBI vs XAUI
I think the specification is quite clear on the XSBI interface.
THere are timing specifications on all 4 interfaces (framer/PCS RX and TX,
plus PMA RX and TX), and a maximum channel skew specification of +/-250 ps.
So, I guess this is quite detailed. The rest is up to the PCB designer to
ensure that all the trace length is approximately within few centimeters of
skew constraints. With a little care a good PCB layouter can do it within
few mm, but a poor auto-router can skrew up everything.
Remember that one bit period at 622 Mbit/s is about 25 cm (in cable) and
1600 ps, so there is plenty of room for sloppiness.
On our evaluation boards we have had something like 3 cm channel skew
(between the slowest and fastest channel), however, there was still about
1000 ps valid timing window (ie. allowed delay variation of the clocks
accompanying the XSBI data signals), when testing with a simple parallel
loop back board.
GIGA, an Intel cmopany.
> -----Original Message-----
> From: Ali Ghiasi [mailto:aghiasi@xxxxxxxxxxxxx]
> Sent: 13. april 2002 06:32
> To: Betancourt, Olivier
> Cc: stds-802-3-hssg@xxxxxxxx
> Subject: Re: [802.3ae] XSBI vs XAUI
> The draft specification does not provide detail clock and
> timing so the
> is limited to about 4-6", but with careful clock and timing design you
> extend the concept of XSBI to over 12".
> "Betancourt, Olivier" wrote:
> > Hello all,
> > This is a simple question. I am wondering if it is possible
> > (practical) to use XSBI as the extension for XGMII instead
> of using XAUI?
> > Thanks,
> > Olivier