Re: [802.3ae] test pattern in cls49.2.8 vs. cls52.9, etc.
Regarding point 2, the ber_count counter used by management is not the
same as the ber_cnt counter used by the state machine. That is why they
have different names. ber_count counter behavior is specified in
184.108.40.206. It is not reset by the state machine. It counts cumulative
bad blocks and is reset only when read by the MDIO. Its purpose is to
allow management to monitor link quality by observing the number of
errors detected. If the link is operating at the objective error rate of
10^-12 it will get about 1 count per hour. Its length was chosen to give
resolution on higher bit error rates given relatively infrequent reads.
Regarding point 3, the title of the sub-clause refers to the correct bit
and the description of the bit's behavior is correct. As you correctly
identified, "2.32.2" on line 54 of P224 and "3.32.2" on line 2 of P225
should both read "3.42.5". This is an editorial errata which we will aim
Regarding point 4, this is a minor editorial error and the normative
description of the counter behavior in sub-clause 220.127.116.11 clearly
describes the non roll-over behavior.
Ben Brown wrote:
>You can get AnAiAnAi or BnBiBnBi from AnAiBnBi by making the
>programmable seed registers identical. You can also select
>between 0 and LF for the data input, regardless of the value
>of the seeds.
>The test pattern generater in Clause 49 is a generic one that
>supports different seeds in A & B or identical ones. The user
>can change these as desired.
>Wei Wang wrote:
>>I've some questions (all refer to D5.0):
>>1) In Clause49.2.8, on p.375, line 5 to 8 says that seeds loaded in pattern of AnAiBnBi, with data input all zero or LF at scrambler. This is not consistent with Clause52.9.1 and Table 52-21, which says the pattern is AnAiAnAi with input data of all-zero, or seed BnBiBnBi with input data of LF. In earlier version (e.g. D4.0) they agree to each other, but lately Clause 52.9.1 was revised. Which one should an implementer follow?
>>2) The ber_cnt is 6-bit counter (Clause 18.104.22.168, p381). But in Figure 49-13, it is reseted after reaches 16. One bit is unused. So is MDIO register bit 3.33.13. Well, no big deal ... I guess totally 6 bits were reserved for ber_cnt in history.
>>3) Clause 22.214.171.124.1, page 224 line 54, "setting bit 3.32.2 to one shall ..." should be "setting bit 3.42.5 to one shall ..." ? Similiar problem in line 2 on page 225?
>>4) Clause 126.96.36.199 Table 45-43 on page 225, the R/W type of the bits register should be changed from "RO" to "RO/NR"?
>>Sr. Logic Design Engineer
>>BitBlitz Communication, Inc.