[802.3] A small query or clarification
I have a small query if some one could address this ( I do not know where
to direct this to the right person ) :
Relates to IEEE 802.3ae /D5.0 may 1 , 2002 clause 48 idle randomizer and
IPG management state machine .
When I look at random integer generator logic(r) in clause 184.108.40.206 IDLE
and the figure 48-5 for
PCS idle randomizer I have a small question ,
a) Is the polynomial to be implemented as x7 + x6 + 1 on a parallel 4 bit
implementation( containing 4 true data bits that
represent this polynomial on all byte clks on 4 bits followed by next 4
consecutive bits of this same polynomial for the purpose
of loading the a_cnt as that is 4 bits . ( this assumes serial clk is
higher rate ) .
b) The x7+x6 + 1 is uses a shift register running on byte clk itself for
all 7 terms with 7 bits and only bits 3-0 ( ignoring rest of the bit terms
are loaded in the a_cnt ignoring the
( top / bottom ) ? ( which one ? ) 3 bits from the generator
whenever a_cnt has to be loaded ?
Query 2) Is a_cnt decremented all time on data as well as idles present
on Xgmii or only during idles & sequences on xgmii ?
if the a_cnt becomes zero in the normal data time for transmission
on the xgmii bus , is that again loaded with the new a_cnt or
is held at zero without loading until idle appears and then loaded
again and decremented only when A is transmitted .
I would appreciate if someone could respond .
Sr Design Engineer