Scramblers, Error Multiplication, and Error Detection (Re: CRC ch eck indication of bad fiber)
- To: "'firstname.lastname@example.org'" <email@example.com>
- Subject: Scramblers, Error Multiplication, and Error Detection (Re: CRC ch eck indication of bad fiber)
- From: "Tim Armstrong" <firstname.lastname@example.org>
- Date: Fri, 21 May 1999 13:01:39 -0400
- Sender: email@example.com
There are three general types of scramblers used in transmission systems,
Frame Synchronous Scramblers (FSS), Distributed Sample Scramblers (DSS),
and Self Synchronous Scramblers (SSS).
The FSS is synchronized by periodically initializing to an agreed state.
The initialization occurs at a time defined by a frame marker. This has
the advantage of quick and robust synchronization (as quick and robust
as the frame marker detection). The disadvantage is some vulnerability
to emulation attacks (made worse by shorter sequences) unless coupled
with another randomization mechanism.
The DSS is synchronized by periodically sending samples of the scrambler
state to the descrambler. The advantage is better randomization when
compared to the FSS. The disadvantage is the time required to acquire
synchronization and the potential for false synchronization due to
random errors in the transmitted samples.
The SSS is synchronized by essentially conveying the scrambler state
within the scrambled data. The advantages are simplicity, very fast
synchronization, robustness against false synchronization, and robustness
against emulation attacks. The disadvantage is the associated error
SSS Error Multiplication
When a transmission error occurs, the SSS will introduce additional errors
equal in number to the number of feedback taps the scrambler employs. For
example, the 1 + x^43 SSS used in ITU-T ATM over SDH/SONET and IETF PPP
over SDH/SONET has a single feedback tap. This means that each transmission
error will result, after descrambling, in EXACTLY one additional error
EXACTLY 43 bit periods after the original error. It is easy to understand
this when you consider what the 1 + x^43 descrambler consists of: it is
just a 43-bit shift register whose input is fed by the received data and
whose output is modulo-2 added to the receive data by an XOR gate. When it
is received, the original error proceeds through the 'data' input of the
XOR gate at the output of the descrambler. At the same time, it is fed
into the shift register. That error will propagate through the shift
register and 43 bit periods later will show up at the 'descrambler' input
to the XOR gate. The corresponding received data bit at the 'data' input
of the XOR gate will be summed modulo-2 with the error to produce a second
error. The error multiplication is now complete. There are no further
errors generated by that original transmission error because the output
of the XOR gate is not fed back to the descrambler. (Only the scrambler
Effect of Error multiplication on Error Detection
Regarding the effect on the detection capabilities of the CRC-32 when SSS
error multiplication occurs, the third reference below contains a good
discussion. This was in the context of PPP over SDH/SONET. Their conclusion:
CRC-32 detection capability is not weakened at all provided that the bit
order of CRC calculation, scrambling, and transmission are aligned.
Other error detection mechanisms could be provided by the PHY layer that
would permit performance monitoring of the fiber. These error detection
mechanisms would have different characteristics to those of the CRC.
Useful references on scramblers for transmission systems and their effect on
CRC error detection capability:
1. S.C. Kim and B.G. Lee,"Low-Rate Parallel Scrambling Techniques for
Lightwave Transmission," IEEE Comm. Magazine, April 1995, pp. 84-95
This gives a good, quick overview of scrambler types, their
and examples of parallel implementations.
2. S.C. Kim and B.G. Lee,"Recent Advances in Theory and Applications of
Scrambling Techniques for Lightwave Transmission," Proc. of the IEEE,
Vol. 83,No. 10, Oct 1995, pp. 1399-1428
This is a more in-depth treatment of the subject of scramblers with
a focus on the theory behind the design of parallel implementations
of the three general scrambler types.
3. D. Ferguson and R. Cherukuri,"Self-Synchronous Scramblers For PPP Over
Sonet/SDH: Some Analysis," IETF
Juniper Networks, November 1997
Section 3.4 discusses the effect of the 1 + x^43 SSS on the error
capabilities of the HDLC CRC-32. This same polynomial is used in
and ATM AAL5.