RE: RE: PHY I/F, placement of decoder/encoder

[Curt Berg <cberg@extremenetworks.com>]

Haim,
I believe both AMCC, Vitesse and HP 
have Quad SERDES devices (4x 1 Gbit),
all with single ended interfaces on the
MAC side. The Vitesse part even comes in 
a 160 pin PQFP. 

-Curt-


-----Original Message-----
From: Haim Shafir [mailto:hshafir@1e9.com]
Sent: Tuesday, May 25, 1999 11:36 AM
To: stds-802-3-hssg@majordomo.ieee.org
Cc: oprescu
Subject: Fwd: RE: PHY I/F, placement of decoder/encoder



Well, there is a problem with that approach
assuming the ASIC can handle the switching
noise, the transceiver can not, the CDR
is very sensitive to noise. If you notice
none of the existing 2.5G chips uses
a single ended interface.



>From: Curt Berg <cberg@extremenetworks.com>
>To: "'Haim Shafir'" <hshafir@1e9.com>, stds-802-3-hssg@majordomo.ieee.org
>Cc: oprescu <oprescu@concentric.net>
>Subject: RE: PHY I/F, placement of decoder/encoder
>Date: Tue, 25 May 1999 11:01:12 -0700
>X-Mailer: Internet Mail Service (5.5.2448.0)
>
>
>I recommend that the PHY interface use a
>signaling compatible with EIA/JEDEC JESD67.
>Basically a "LVTTL" that is can configured
>for different VDD voltages. If we also
>mandate an impendance matched/controlled driver,
>+/- 10%, unterminated point to point <12 inch traces, 
>we should easily be able to do 300+Mbaud per wire.
>
>-Curt-
>Extreme Networks, cberg@extremenetworks.com
>
>-----Original Message-----
>From: Haim Shafir [mailto:hshafir@1e9.com]
>Sent: Tuesday, May 25, 1999 9:49 AM
>To: stds-802-3-hssg@majordomo.ieee.org
>Cc: oprescu
>Subject: PHY I/F, placement of decoder/encoder
>
>
>
>Currently the 8/10B encoder/decoder
>is located in the PHY. 
>
>But :
>
>The current implementation of 2.5Ghz and 10Ghz
>do not have those function on board
>In addition the current chips are GaAs, Bipolar 
>or SiGe ( in the near future )
>If you place more logic on those chips you will
>burn a lot of power, with 4 channels you could fry
>and egg. ( those chips already burn Watts )
>
>So we strongly suggest that any decoding/encoding/
>alignment function should reside on the ASIC side.
>
>Now the next big problem is the interface
>if we run it at 2.5/8 or 2.8/10 times 4
>we will have 32 lines single ended
>or 64 differential. The current diff interfaces
>all burn tons of power , LVDS , PECL all are power hogs.
>
>With single ended you get bad switching noise
>the ASIC can handle it but I am not sure about
>a 4 port transceiver.
>
>We may want to look at CML type interface.
>But again we need to look at current implementation
>( at no preferred order : AMCC, Vitesse , Maxim ... )
>and check what is available out there and also
>see what is available on the ASIC side.
>
>
>
>
>
>Haim Shafir
>e9 Inc.
>PH 408-343-0192 cell 408-892-1838 fax 408-873-2642
>hshafir@1e9.com

Haim Shafir
e9 Inc.
PH 408-343-0192 cell 408-892-1838 fax 408-873-2642
hshafir@1e9.com