CMOS in Serial PMD
The following questions needs to be answered before
PMD proposals can be rated against the PHY/PMD
evaluation criteria:
1) Somewhere inside a serial PMD the is a N:1 10 or
12.5 Gb/s MUX. This requires the N inputs to be
registered at the same clock (i.e. jitter + skew +
setup/hold-time < 1 UI, setup+hold-time approx. 150 ps
in a realistic high speed mux). Since UI = N/LR (LR =
Line Rate), the skew out of a device driving the N:1
mux determines the minimum width N. WHAT IS THE
MINIMUM GUARANTEED SKEW BETWEEN INDIVIDUAL 3.1 Gb/s
CMOS OUTPUTS?
2) Assuming the 4 bit serial interface proposed by
Howard Frazier, all PMD's will contain a CMOS chip for
management and to take the 4 bit serial into something
useful to the rest of the PMD (e.g. N:1 MUX/1:N DEMUX
or jitter clean-up for WDM). HOW MUCH POWER WILL SUCH
A 4-BIT SERIAL CONVERTER CHIP DISSIPATE?
I hope the answers to the questions above will
generate new PHY/PMD proposals and alow them to answer
to the evaluation critiria.
Henning Lysdal
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