RE: SONET/Ethernet clock tolerance
Tim,
Thank you for the precise information. I agree that we can cut off
most of the overhead access in your WAN-PHY with SONET framer. Thanks
to your illumination, I realized that I should estimate the consumption
power of each function block in our SDH VC-4-16c (2.5 Gb/s) Line
Terminating Chip.
Here are the rough estimation by my colleague Kenji Kawai of NTT who
designed the chip;
25% Pointer Manipulation & Memory holding during overhead periods
30% Full Overhead access
45% Clock distribution in the chip
He excluded the consumption power for chip I/O and hence the above
100% nearly equals 1.5 W. Note that we have implemented very heavy
extra DCC bytes (D13-D192), and hence the 30 % should be overestimated.
From this evaluation, at least in our design and process, we will have
relatively small impact of reduced overhead access on the total
cosumption power for the SONET line termination.
I am not sure that the result on our chip could be fair or not.
Any additional information on this matter would be appreciated.
Best Regards,
Osamu
At 3:20 PM -0400 00.4.11, Tim Armstrong wrote:
http://grouper.ieee.org/groups/802/3/10G_study/email/msg02260.html
> Osamu,
>
> Regarding the subset of SONET/SDH overhead functionality required
> by the proposed WAN-Compatible PHY: this has been described in
>
> http://grouper.ieee.org/groups/802/3/ae/public/mar00/figueira_1_0300.pdf
>
> and, in greater detail, in
>
> http://grouper.ieee.org/groups/802/3/10G_study/public/nov99/figueira_2_1199.pdf
>
> Some of the functions that are NOT needed by the WAN-Compatible PHY that
> would normally be required by STS-192 PTE are (the most significant are marked
> with an asterisk):
>
> Section Orderwire (E1) insert / extract
> User Data (F1) insert / extract
> Section DataComm (D1-D3) insert / extract
> *383 STS pointer processors
> (192 in each of Tx and Rx direction normally required)
> *384 Line BIP-8 (B2) generators
> (this is a big chunk: > 6144 bits of high-speed storage)
> *192 Line BIP-8 extract / compare and B2 mis-match accumulator
> (~ 1600 bits of storage)
> Line APS bytes (K1/K2) extract / validate
> Line DataComm (D4-D12) insert / extract
> Synchronization Status Message (S1) extract / validate
> Line REI (M1) extract / accumulate
> Line Orderwire (E2) insert / extract
> Path Trace (J1) extract / message assembly / Trace Mismatch compare
> Path BIP-8 (B3) modification to support Tandem Connection
> Path User (F2) insert / extract
> Path Multiframe (H4) insert / extract
> Tandem Connection Maintenance (N1) insert / extract
>
> In addition to these data-path insert / extract functions are the
> corresponding processing functions and management registers, which
> are also NOT required.
>
> Conversion to power-dissipation/gate-count/etc will depend on
> partitioning and process.
>
> Tim Armstrong
> Nortel Networks
-----Original Message-----
From: Osamu ISHIDA [SMTP:ishida@exa.onlab.ntt.co.jp]
http://grouper.ieee.org/groups/802/3/10G_study/email/msg02245.html
> At 4:56 PM -0500 00.4.10, Tim Armstrong wrote:
http://grouper.ieee.org/groups/802/3/10G_study/email/msg02241.html
-----------------------------------------
Osamu ISHIDA
NTT Network Innovation Laboratories
TEL +81-468-59-3263 FAX +81-468-55-1282