Re: XAUI IO specs
Rich,
Thanks for the link to the presentation. I have been looking for that
presentation for a couple days. It makes things clear to me.
http://grouper.ieee.org/groups/802/3/10G_study/public/nov99/ghiasi_1_1199.pdf
It looks like Ali did a fine job of defining signaling. Looking at the
LVDS levels in the table on page 12, it looks like no signals are referred
to a peak-to-peak need not be defined that way. In fact the first four
items in the LVDS column match the IEEE spec.
It appears by the data in the Hari column that it is a custom I/O signaling
level designed to launch 4x the power (2x voltage and 2x current) into the
trace, counting on attenuation of up to 9.1 dB with "normal" FR4, and still
having about the same signal as required at the receiver end of IEEE LVDS.
I also agree with the deviation from tight termination tolerances in IEEE
LVDS spec, allowing us to integrate the receiver termination resistors.
I also looked at the picture on Page 13 of Ali's proposal, and noticed that
you referred to the 0V in the picture as ground. The 0V above the X1 point
is 0V differential and has nothing to do with ground. Now my head doesn't
hurt any more.
Kevin Demsky
Mixed Signal and VLSI Development
IBM Corp.
3605 Hwy 52 N
Dept. QXS Bldg. 050-2
Rochester, MN 55901
Internal E-mail: kdemsky@ibmusm07
External E-mail: kdemsky@us.ibm.com
Phone: 507-253-5799
Fax: 507-253-4966
>Mike,
>On your P.S., I was referencing slide 13 from the proposal authored by Mr.
Ali
>Ghiasi and Mr. Richard Dugan presented at the November '99 HSSG meeting in
>Kauai, HI:
>http://grouper.ieee.org/groups/802/3/10G_study/public/nov99/ghiasi_1_1199.pdf
>The legends on the Y-axis come from the table on slide 5. Note the
reference to
>0V, or ground on slide 13.
>Best Regards,
>Rich