RE: XGMII
Single clock, GOOD.
Sharam
> ----------
> From: Claus Stetter[SMTP:cstetter@allayer.com]
> Sent: Tuesday, July 18, 2000 5:32 PM
> To: Roger Ronald; 802.3ae
> Subject: Re: XGMII
>
>
> Hi Roger,
>
> I fully agree with your statement. Why add additional pins to an already
> wide interface and add the complication of synchronization when it can be
> done with relative ease with a single reference clock? Several companies
> that I know of are implementing XGMII as presented and have not had issues
> with the proposed timing spec.
>
> If it ain't broke, don't fix it ;-)
>
> Cheers,
> Claus
>
>
> Claus Stetter
> Allayer Communications
>
> Tel: +1 408 570 0888 x170
> Fax: +1 408 570 0880
> Cell: +1 408 221 6461
>
> Email: cstetter@allayer.com
> http://www.allayer.com
>
> ----- Original Message -----
> From: Roger Ronald <rronald@pmr.com>
> To: Justin Gaither <jgaither@rocketchips.com>; 802.3ae
> <stds-802-3-hssg@ieee.org>
> Sent: Tuesday, July 18, 2000 4:26 AM
> Subject: Re: XGMII
>
>
> >
> > This interface does not seem to be any harder than interfacing to DDR
> RAM
> > at the same speed. Every corner garage shop will soon be turning out
> > DDR RAM based motherboards soon.
> >
> > Personally, I'd much rather have relatively tight timing instead of
> > complications in the clocking and a whole new chip to chip
> > protocol to spec/understand/debate/document/build.
> >
> > RR
> > ----- Original Message -----
> > From: "Justin Gaither" <jgaither@rocketchips.com>
> > To: "802.3ae" <stds-802-3-hssg@ieee.org>
> > Sent: Monday, July 17, 2000 3:15 PM
> > Subject: XGMII
> >
> >
> > >
> > > Everyone,
> > >
> > > Concerning the XGMII interface, I remember at least one comment
> > > during the plenary and I have the same reservation concerning the
> > > extreme width and tightness of the setup and hold timing.
> > >
> > > I would like to suggest separate clocks for each of the 8 bit lanes.
> > > This would allow each lane to have a manageable number of tightly
> > > coupled signals, and allow for 1 or two clocks skew between lanes.
> The
> > > Bus could easily be spread across the pins of a device enabling
> > > distributed reference and less ground bounce. I don't see adding 3
> more
> > > pins to a 37 pin interface to be excessive. Synchronization of the
> > > lanes could be done using the control lines for a sync. (i.e.. 1111
> > > followed by 1000 on the control is start of data).
> > >
> > >
> > >
> > > --
> > > Justin Gaither Phone: 512-306-7292 x529
> > > RocketChips, Inc. Fax: 512-306-7293
> > > 500 N. Capital of TX Hwy.
> > > Bldg 3 email: jgaither@rocketchips.com
> > > Austin, TX 78746 WWW: www.rocketchips.com
> > >
> > >
> > >
>