Re: FW: XGMII Clocks
Sanjeev,
Clock edges moving back and forth, especially from multiple independent
clock signals are not a good thing.
I don't see how a two-phase clock solves the duty cycle problem. The
source clock starts out with a duty cycle proble due rise and fall time
differences of a 156.25 MHz (or less reference clock) and the
requirement to clock on both edges (DDR). Then you generate two phases
of the clock (implementation dependent) and output the clocks as two
single-ended clocks 180 degrees out of phase. The result is two
independent clocks, both of which have approximately the same amount of
DCD.
Tightly specifying the DCD component would only add to the
implementation cost of this interface.
I agree that a differential DDR XGMII clock is preferable to a two-phase
clock. My understanding is that a two-phased DDR XGMII clock is the
worst possible proposed solution for XGMII clocking.
Best Regards,
Rich
--
Sanjeev Mahalawat wrote:
>
> Rich,
>
> At 10:07 AM 09/07/2000 -0700, you wrote:
> >
> >Forwarded in behalf of Rich Taborek.
>
> >> 2) Changing to a two phase clock: This doesn't help with duty cycle
> >> variation at all and nominally makes it worse.
>
> The two phase clock do releive the duty cycle problem.
> Because with one varying duty cycle clock the
> data tracks with the edges but only one edge of the
> clock moves back and forth. And that will shrink one data valid
> window and stretch the other data valid window in one clock period.
> So with min pulse width the hold time will suffer
> and with max pulse width setup will suffer.
>
> And this also means that the duty cycle variation
> of the clock have to be very tightly specified.
>
> Thanks
> -Sanjeev
>
> >jonathan
> >
> >> -----Original Message-----
> >> From: Rich Taborek [mailto:rtaborek@earthlink.net]
> >> Sent: Wednesday, September 06, 2000 9:44 PM
> >> To: Jonathan Thatcher
> >> Subject: Re: XGMII Clocks
> >>
> >>
> >> Jonathan,
> >>
> >> Can you post the following note to the HSSG reflector for me? I've
> >> posted it twice today and neither copy made it to the
> >> reflector. I never
> >> got my copy and it's not in the archives.
> >>
> >> --
> >>
> >> Howard, et. al.
> >>
> >> My simple-minded 2 cents about XGMII clocking:
> >>
> >> 1) The way it is: The XGMII baseline defines single-ended
> >> data lines and
> >> clocks in both data directions. The clocks are DDR and are subject to
> >> duty cycle variations. The primary benefit of using DDR
> >> clocks seems to
> >> be EMI. The I/O buffers for data and clock would seem to track (i.e.
> >> cancel) each other over process and temperature.
> >>
> >> 2) Changing to a two phase clock: This doesn't help with duty cycle
> >> variation at all and nominally makes it worse. EMI would be
> >> worse since
> >> there are twice as many of the same EMI sources. Seems to be a
> >> disadvantage to the way it is. For this disadvantage, the cost is one
> >> extra pin.
> >>
> >> 3) Changing to a differential clock: The source of the differential
> >> clock is likely to be single-ended with duty cycle variations. The
> >> resultant differential clock would be subject to the same duty cycle
> >> variations as a two phase clock. Since the I/O buffers for data and
> >> clock would be different, the inherent tracking of data to clock would
> >> be worse. I'm assuming that what is meant here is that only the clock
> >> would be differential, not the data. Otherwise, double the number of
> >> XGMII signals to 148 from 74. I know of no other standard or proven
> >> interface where the data is single-ended and the clock is
> >> differential.
> >> Seems to be a disadvantage to the way it is. For this
> >> disadvantage, the
> >> cost is one extra pin.
> >>
> >> 4) Precise phase positioning: This is essentially what Joel Dedrick
> >> suggested in his reply to this thread. It requires a PLL on
> >> one or both
> >> side of the XGMII interface to sort out where to sample the data. This
> >> does NOT mean that an XGXS or XAUI is required. It just so
> >> happens that
> >> the XGXS implementation contains one or more PLLs. This
> >> technique would
> >> be applicable to XGMII DDR, two phase, or differential clocks.
> >>
> >> Bottom line is that a DDR clock seems adequate and when stretching
> >> things, one may need to add a PLL or two to ensure interface
> >> robustness.
> >>
> >> Best Regards,
> >> Rich
> >>
> >> --
> >>
> >> Howard Frazier wrote:
> >> >
> >> > In a previous email thread, we debated the merits of using
> >> > a single clock in each direction on the XGMII, versus using
> >> > 4 (frequency locked, but phase independent) clocks in each
> >> direction,
> >> > with a clock dedicated to each of the four "lanes".
> >> >
> >> > Without repeating the discussion, it is safe to summarize that
> >> > the majority opinion (from among those who expressed an opinion)
> >> > was to stay with one clock in each direction.
> >> >
> >> > So, I would like to toss out another question for your
> >> consideration.
> >> >
> >> > Should we use a two phase clock? Clock and ClockBar?
> >> >
> >> > Some designers have suggested that this will make the ASIC and
> >> > system timing more managable, because it is difficult to get
> >> > symetric drive strengths from the clock output buffers, and
> >> > the asymetry degrades the timing. With a two phase clock, you
> >> > would still have asymetry on the data signals, but at least
> >> > you won't have to account for the asymetry on the clock.
> >> >
> >> > At first blush, this seems like a modest addition. One more pin
> >> > in each direction.
> >> >
> >> > Any opinions out there?
> >> >
> >> > Howard Frazier
> >> > Cisco Systems, Inc.
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