RE: XAUI receiver characteristics
Bijit and all,
I think that the minimum pulse width is slightly less than 0.59UI. I get
this by only considering the deterministic contribution of 0.41UI to eye
closure and neglecting the random jitter contribution to a single bit pulse.
This is equivalent to assuming that the jitter energy is small at high
frequencies. I think this is a practical reality for several reasons. First,
it is unlikely that transmitted random jitter will be concentrated at high
frequencies. (There is nothing currently in the standard to prevent someone
from building a transmitter that puts most of the random jitter energy near
the baud rate, but it would probably require an intentional effort!) Second,
reflections introduce random jitter for long channels, but they are down by
almost 40dB after the round trip. Third, differential noise balance and
noise immunity are expected to be good. Have I missed any significant
sources of random jitter with high frequency content?
Another way to describe this is to realize that the minimum receive eye
width is 0.35UI with random jitter and the random jitter contribution is 14
* 5.49ps = 77ps = 0.24UI. Then the opening without random jitter is 0.35UI +
0.24UI = 0.59UI. This is the opening that is left after DJ, which is
determined by the single bits. (In the absence of random effects, the inner
traces defining the eye opening are due to single bit pulses such as five
zeros followed by a one and a zero, or the inverse.
I am not an expert and could be missing something. Feedback is welcome! This
is a little difficult to discuss via e-mail so feel free to call.
-Dawson Kesling
Intel Corporation
916 855-5000 ext. 1273
-----Original Message-----
From: Bijit Patel [mailto:Bijit_Patel@pmc-sierra.com]
Sent: Wednesday, October 18, 2000 8:57 AM
To: 'Kesling, Dawson W'; HSSG
Subject: RE: XAUI receiver characteristics
Dawson,
It seems that there is a lot of confusion as to what the minimum
pulse width should be at the receive end. If one just looks at the
eye-opening of 0.35UI, it would imply a minimum pulse width of 112ps which
I believe is unrealistic since eye-diagram is a superposition of multiple
bits (edges).
I think we need to define the minimum pulse width at the receiver in the
standards document along with the eye-diagram. The question is what value
should
one use for the minimum pulse-width.
If one uses minimum-pulse of 112ps and assumes that the clock is in the
middle
of the data-eye, it would imply a setup/hold time of 56ps for the Flip-flop
that latches the data. This is surely extremely difficult to do in standard
CMOS.
Any thoughts/comments on this.
Thanks,
Bijit
-----Original Message-----
From: Kesling, Dawson W [mailto:dawson.w.kesling@intel.com]
Sent: Tuesday, October 17, 2000 8:52 PM
To: HSSG
Subject: RE: XAUI receiver characteristics
Anne,
>I think it might be also beneficial to define what pk-pk jitter is at
>the receiver from one bit to the next, i.e. at high frequencies -
>3.125G/2. Does it mean that:
>
>1. A single received bit can shrink to 0.35UI - 112 ps? (not surely
>practical given the transmitter spec?)
You are right. This is not possible given the transmitter spec.
>or
>
>2. Over a pair of received bits, one bit can shrink to 67.5% of nominal
>bit (216 ps) and the next bit can stretch to 132.5% of a nominal bit
>(424ps), giving an overall jitter between the pair of 0.65 UI? Another
>way of describing this is a receiver must successfully land a single
>occurrence of a 1 as long as 132.5% or as short as 67.5%. This leads to
>a definition of pk-pk jitter as
>
> (maxBitTime - minBitTime)/nominalBitTime e.g. 132.5-67.5/100 = 65%.
Also not possible given the transmitter spec.
>An eye diagram builds up an aggregate picture over many thousands of
>bits. If in that sample size, one bit stretched and another bit shrunk
>by half pk-pk jitter, it would result in an eye opening of 0.35 UI. It
>would not necessarily mean however that any bit had shrunk by 0.65 UI.
Right. This is the intent of the receive eye.
>A jitter mask describing amplitude of jitter versus frequency from 100hz
>to 3.125G/2 would be helpful.
There is some desire to avoid a full jitter immunity plot verses frequency
if possible due to the compliance testing burden. Even a SONET-like immunity
plot has a flat tolerance out to the baud rate and doesn't eliminate the
112ps pulse scenario.
If the intent is to avoid a misinterpretation of receive eye compliance
requirements, then I would prefer to see a statement such as, "The source
for receiver compliance testing must comply with the transmit
specifications. A linear filter can be used between this source and the
receiver for compliance testing purposes." I haven't thought enough about
how to word and incorporate this into the standard, but the purpose is to
prevent someone from generating a 112ps pulse and expecting the receiver to
comply. In effect, it limits random jitter to 0.35UI (plus a little for
noise) and budgets the rest to DJ. This is more like the real world
situation. Any thoughts?
>- Anne
-Dawson